File: //sys/kernel/btf/mlx5_ib
�� �� �� ,� �& H �$ ' @ ' � � ' � � $' �k *' � @ f � � � �k � 2' = <' � @ G' � @ T' � @ e' � @ s' � @ ~' � @ �' � @ �' � @ �k
G �k E �k �P( �P( �P( �P( Q( Q( v � �M �a vl @ 4Q( � � }~ �| � BQ( xl � � ; UQ( # � fQ( � � tQ( ; }Q( � � �Q( ; � �Q( ^ �5 � @ �Q( � � �k
(o �k
'p } } �k �k � � �k Å �Q( �k �9 �k �
�k �k �k
Z| f} �k �k ʅ ` �l /1 �l �k
�| �| �k �k
�| <| �| �k �k
�| 'p �| �} �k �k
�| �k �k
�| �| �| �} �k �k
�| �k �k
�| �} �k �k
�| �k �k
�k �k U� � F� �l �l @
�k �k �Q(
�Q( �Q( �Q( -O � + �Q( + 0 �� �
@ � + � l� + � �Q( , � � � R( R( 8R( MR( fR( }R( �R( �R( �R( �R(
�R(
S(
)S( HS( ]S( tS( �S( �S( �S( �S( T( T( 3T( LT( oT( �T( �T( �T( �T( �T( U( U( .U( DU( [U( pU( �U( �U( �U( �U( �U( �U( V( *V( >V(
RV( gV( ~V( �V( �V( �V( �V( �V( W( W( 9W( UW( oW( �W( �W( �W( �W( �W( X( X( 7X( MX( aX( % �X( & �X( ' �X( ) �X( * Y( @ #Y( P AY( Q `Y( R �Y( S �Y( T �Y( U �Y( ` Z( a .Z( b RZ( c wZ( d �Z( e �Z( o �Z( p �Z( q [( r -[( s I[( t i[( u �[( � �[( � �[( � �[( � \( � 6\( � \\( � ~\( � �\( �\( �\( �\( �\( ]( 4]( N]( j](
�](
�]( �]( �](
�]( �]( ^( :^( _^( " }^( # �^( $ �^( % �^( & �^( ' _( ( >_( ) ]_( * ~_( + �_( 0 �_( 1 �_( @ �_( A `( B `( C .`( D K`( E i`( �`( �`( �`( �`( �`( �`( a( a( 3a( Ia( ka(
�a( �a( �a(
�a( �a( �a(
b( !b( 9b( Ob( fb( }b( �b( �b( / �b( 0 �b( 1 c( 2 %c( 3 Cc( 4 bc( 5 c( 6 �c( 7 �c( 8 �c( 9 d( : 'd( ; Fd( < dd( = �d( > �d( ? �d( @ e( A 6e( B ^e( ` ye( a �e( b �e( c �e( d �e(
f(
1f(
Rf(
uf(
�f(
�f(
�f(
�f( �f(
g( ,g( Dg( hg( �g( " �g( # �g( � �g( G �g( � 0 �g( � 8 �g(
@ h( � � 0h( G_ � ?h( � � Uh( � _h( � {� � }h( � �h( � �h( � ( �h( � 0 �h( � 8 i(
@ !i( � � )i( � 8i(
Gi(
@ Ui( � � _i( } � ni( � � �i( ) � �i( � � �i( } � �i(
� �i( � �i( � �i(
�i( � H �i( � P j(
X j( � � j( � � ,j( � � ?j( G � Nj( � � Xj( G � gj(
�j(
@ �j( � � �j( � � �j( � � �j( � � �j( � � #k(
� .k(
<k( � @ Sk( � H uk( G P �k( G � �k( � � �k( � � �k( � � �k( } � �k( � � �k( ) � �k(
l( � @ l( � H #l( � � 2l( � � Bl( G � Xl( � � xl( � � �l( G � �l( } �l( � �l( � �l( G P �l( } � �l( � � �l( G �
m( � � m( G � 0m(
@m( � (
Rm( � 0
_m( } 8
om( � H
ym( G P
�m( � �
�m( G �
�m( � �m( � �m( � �� � �m( � �m( ) ( �m( � H n( } P &n( � ` :n( � h Dn( � p Tn( � x ]n( � � ln( � {n( � �n( � �2 � �n( � �n( � ( �n( � 0 �n( � � �n( �
�n( �
o( �
o( �
o( �
6o( � (
:o( � 0
Io( � 8
Yo( � @
go( � H
po( � P
ac
X
yo( � �
�o( � �
�o( � �
�o( � �
�o( � �
�o( � �
/� } �
Jq
�
�o( � à � �o( � �o(
p( ) @ p( ) ` p( � � �� � � *p( � � Ep( } � Up( � � Zp( � � `p( � � fp( � � vp( � � |p( � � �p( � � �p( � � �p( � � �p( � � �p( � � �p( � �p( � � �p( � � �p( G � �p( � �
q( } � q( � � :q( ) � Fq( � ]q( � iq( � yq( � �q( � �q( � ( �q( � 0 �q( � 8 �q( � @ r( � H $r( } P .r( � ` Cr( } h Sr( � x `r( } � or( � � zr( � � �r( � � �r( � � �r( � � �r( � � �r( � � =L � � �r( � � gi � � �r( � � #k � � �� � � �r( � � �r( � �r( � �r( � s( � s( } &s( � 0 � � 8 2s( � @ >s( � H Ns( � P ds( � X F
� ` }s( � h �s( � p �s( � x �s( � � �s( � � �s( � � �s( � � �s( � � �s( � � �s( � � �s( � � so � � �s( � � �� � � ʚ
� � �s( � t( � t( � @ -t( � H ;t( G P Bt( � � Ut( � � at( � � lt(
� |t(
� �t( � R
� �t( � �t( � �t( � 0 �t( ) 8 �t(
X �t( � � �t( � � �t( } �
u( } � u( � � 'u( � � @u( � � Pu( � � [u( ) � iu( � yu( � � �u( m~ �u( � X �u( ) ` �u( � � �u( � �u( � � �u( � �u( �~ 8 �u( � v(
� 'v(
� 3v( � Cv(
\v( } @ lv( � P �v(
X �v( � � �v( � � �v( � � �v( � � �v( � � w( � � "w( � � Lw( � � gw( � � �w( � � �w( � � �w(
� �w( � �w( � �w( � x( � "x( � 2x( � ( Hx( � 0 ]x( � 8 mx(
@ �x( � � �x( � �x(
�x( � @ �x(
X �x( � � �x(
� �x( � � �x(
� y( � y( } 0y(
<y( � @ Ly(
X Xy( � � hy(
� yy( � � �y(
� �y( � �y( � �y( � �y(
�y( � @
z(
X "z( � � 2z(
� Gz( � � Wz(
� lz( � tz( } �z(
�z( � @ �z(
X �z( � � �z(
� �z( � � {(
� {( � '{( � ;{( � O{(
j{( � @ z{( � H �{( � P �{(
X �{( � � �{(
� �{( � � �{(
� �{( � |( } " |( } " |( ) " 7|( � @" L|( � # \|( � # `|( � # o|(
# ||( � @# � � H# �|( � P# �|(
X# � � �# �|( � $ �|( � $ �|( � $ �|(
$ �|(
@$ �|( � �$ �|( �
% }( �
& }( �
' 0}( �
( @}( �
) U}( �
* k}(
+ �}( � @+ �}(
X+ �}( � �+ �}( � �+ �}( G �+ �}( m~ , �}(
X, ~( � �, ~(
�, <~(
�, L~( � - \~( � �- u~( � �- �~( � �- �~(
�- �~( ) �- �~( � �- �~( � �- �~( � �- �~( � �- ( � . ( � �. 2(
/ B( ) @/ [( ) `/ wo � �/ k( � �/ {( � �/ �(
�/ �( � �/ �(
�/ �(
0 �(
@0 �(
�0 �( ) �0 �( } �0 %�( � �0 1�( � �0 A�( � 1 ]�( � �1 x�( � 2 ��( � �2 ��( �
3 ~=
� 4 ��( � 4 ��( � 4 ˀ(
4 ր( � @4 ڀ( ) H4 �( � h4 �( } p4 �(
�4 �(
�4 *�( �
5 3�( ) 6 C�( ) 6 f�( ) @6 ~�( ) `6 ��( ) �6 ��( ) �6 ʁ( ) �6 �( ) �6 "�( � 7 8�( � �7 C�( ) 8 \�( ) 8 �( � @8 ��( � 9 ��( � �9 ��( � : т( ) `: �( } �: �( � �: �( � �: �( � �: ;�( � ; K�(
; n�( ) @; ��( ) `; Ã( � �; Ӄ(
�; ��(
�; �( � < �( � > <�( � K# � �6 � � X�( � g�( � �( � v�( G_ !i( � � ��( �
�g( � @ � �
�k( �
��( �
xl( �
�k( �
�k( �
�i( �
��( � K# � �( � � X�( � �( � � )i( � ��( � K# � �( � � X�( � �( � � )i( �k �( ) � '�( �
6�( � �
�g( � @ � �
)i( � P�( � d�( � K# � �( � � X�( � �( � � }�( � ��(
� �
� '�( �
��( � ��( K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( : ˅( � K# � �6 � � X�( � �( � � )i(
�( � @ '�( �
�( � K# � �6 � � X�( � �( � � )i(
�( � @ '�( �
�( � K# � �6 � � X�( � �( � � )i(
,�( � @ '�( �
1�( � K# � �6 � � X�( � �( � � )i(
Ah � @ '�( �
O�( � K# � �6 � � X�( � �( � � )i(
l�( � @ '�( �
p�( � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( � K# � �6 � � X�( � �( � � )i(
7 � @ '�( �
dž( K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( : �( � �
�g( � @ � �
)i(
Ah � @ '�( �
�( � K# � �6 � � X�( � �( � � )i( � �( � �
�g( � @ � �
)i(
l�( � @ '�( �
;�( � K# � �6 � � X�( � �( � � )i( � V�( � �
�g( � @ � �
)i(
��( � @ '�( �
�( � K# � �6 � � X�( � �( � � )i( � ��( @ � &� � kv , ��( �
@ ;� M � >� M ��( �
� �H , � � � � X3 � Ƈ( � ч(
@ ߇( t� &� 38 � �( , ��( , X3 �z @ � , ` Xa , � � , � �( � s3 � � �( � A � !�( + � *�( 8�( , ?�( , &� 38 @ P�( , � \�( , � k�( , � X3 �k � u�( , � �� �k s3 �k ��( , � ��( , � ��( , � ��( , � �5 38 @� ��( , �� 7 �k �� ͈( , � و( , � �( �k @� �( �
��( , @
�( , ` , x , n , , � �( !�( 2�( M�( Z�( j�( x�( ��( ��( ʼn( �( �( ��(
�( #�( 4�( I�( V�( n�( ��( ��( ��( ��( ��( ӊ( % �( & �( ' �( � E i� � �( .�( ?�( N�( a�( ����u�( ��( ��( ��( ��( * � �a Z ŋ( �k @ z� �
� ҋ( � � �( +l � �( � ��( � � aQ �k �� :l @ � Al : _a @: ��( �: �( Bl �:
�( ; f *l @; �( � �; }| � �< '�( �< W l �< �� 6l @[ 2�( @a 7�( .l �a �u Dl �n � Fl �n A�( Hl o #k ?l @o Up( Jl @p �4 4l �p H�( Ll �~ �� Nl S�( Pl @ \�( � e�( Rl � ,� Tl � m�( @� z�( �� ��( Vl �� ��( F � ��( �� Z` Xl �� ��( 9l � ��( � @� �k Ȍ( ٌ( ��( �( "�( �9 M 1�( 8 � ; �k � � � �k � � �k � >�( � �? ; @ L�( � [�( � �k c�( �] E 6� � @ � �k � �k t�( z� G �� E @ �� E � � � kv � �H � X ��( ��( ��( ��( � @ T= �c � ��( �c @ ��( �c Í( � � �k 9\ �k f �k � ̍( E ڍ( � @ E� � �!
E � 6� � � � @ �( � ` � � �( 3 � G 2 � � ��( �( �k @ �� �* @ �( �k � �� �k � �( � / � � �k �k $�( P f ;� \l @ >� \l � 6�( E � ;�( CG Yl @ E�( 1 � �S E @ �� � M� � U�( � n< � aQ ]l � J � ]�( ^l �� @ a�( ` � � � � l�( � p�(
�] @
�� . P
�, � `
�k t�( P u E �g . @ 6 ` � ; � ��( ��( T @ ��( T � ��( � ��( � � �a �k @ ��( 0 � � ; ( ` Ҏ( �k ێ( �k � �( u E � �k @ �g . � 6 � � � �k �( �� �k ��( �@ @
G � � � �( � A �( �( @ G 2 � 1 � '�( � 9�( � E�(
- Q�(
- @ c�(
- � q�( 1 � �k ��( �P b( ��( @ 5R � ��( � ��( � R �k � �i F ��( я( �k ��! @ �� ` ُ( p �k �( �@ �( � 3 � 6 � �6 � ��( � �( @ �( � � jR aR @ �( �k � 3 � �k "�( �� �k �� l @ 1�( l � <�( �k L�( �k \�( l m�( X �� =U �a �k @ �� � w�( 8 z� G ��( G @ ��( G � ��( G � ��( G ��( G @ ɐ( G � Ր( - � ߐ( l �( l @ �( �k � ��( 2 � ��( � � �( 8 @ -W ; � �( �( L ,�( � B�( � U�( �� �k @ [� ; � �( l @
k�( � �b w�( � @ ��( ; @ ��
l � ��( ��( �4
l @ ��( l � ��( l � ��( l ��( l @
� �k � )
l 1 @ đ( l � ɑ( l � ّ( l #k �k @ �( l �( �k @ �( !l @ ��( �k � l�( �k � ��( #l � �( %l �( �k @ )�( 'l � 5�( )l � >�( F E�( l T�( l l l b�( l n�( l �( l ��( l ��( l ��( l ��( l ( l ג( l �( l �( l �( "l �( $l +�( &l <�( (l J�( \�( q�( ��( ��( ��( ӓ( 8 �` � ۓ( ; �( � �( p �~ ,l @ ��( ��( �k @ �( l @ �( . @
�( � �( -l %�( � � 3�( � � F�( 0l � O�( /l d�( �1 � � @ s�( � |�(
��( � @ �1 �
@ b( @ ��( � ��( � ��( P �� h �P h � Ô( Ҕ( @ �( � �( �k � ��
D� @ F� >h � �( h ��( 2l �
G 3l � �B �( � )� �i( @ �( H "�( 7l ` 5l +�( �h �+
�+ � 8�( F�( b�( |�( � ��( ;l ��( d � ��( =l @ Up( l @ ��( >l @ ��( � <l ' 8l H ��( 1l ( � ʕ( @l �k ؕ( 0 E_ �k � @ �( 7 � Cl �( El ��( Gl �( Il �( 8 � l� �M @ �� � l� � �X �X )� @ Ҕ( � Kl -�( Ml <�( Ol J�( Ql W�( Sl b�( Ul q�( Wl y�( Zl [l
E �k �k �k ��( 0 E_ �k ��( 8 @ ��( � ��( `l ��( ˖( ޖ( �( �( @ �( fl *�( hl @ 7�( hl � C�( jl � N�( ll Y�( nl @ d�( hl � r�( pl �
cl
�| �k �k el
�| gl
�| �k �k bl il
�| bl kl
�| �k �k ml
�| �| ol ��( ��( tl _� 3 @
ql dl
sl ��( ul ��( wl � �� � �Q Ǘ( ٸ yl [n zl ї( {l � �l ڗ( � � �( ��( �(
�( �� |l � �l @
~l l � �� 1 �Q 0 ї( }l �( �l $�( . �2 ~l @
�l 4�( . 1 �� 3 @ /1 �l � �i �l �
�l �l �l
�l �l
�k �l F�( . X�( �l @ c�( 3 � Ю �l �
�l rl �l �l
�l �l o�( � y�( ��( ��( ��( :c Cc ��( �l p- �l ��( �l ��( �l �� �k Ș( �l ט( 3
. 'p �l �l ٸ E �9 �( �l � @ ��( P �( ` �( �g �| �( �l @ "�(
�l �l 2�( tQ( �l � @ �| G�( �l P�( �l Y�( �l g�( �l ` s�( �| ��( �| v �k �S �| @ �g �| � ��( � � ��( ` s�( �| ��( �| v �k �S �| @ �g �| � ��( � � ` �l 0� �l �l ��( ( � E 1d � � ��( @ � E Ǚ( � � � @ �� � � Ι( 0 �� �k ݙ( l @ �( l � �( l � �( l
�( @ !�( @ �P �k �f �l @ 3 � 3�( 5 �� [} �{ �a �k \ ?�( �l @\ O�( � �\ `�( E �] l�( E @^ Jq _ w�( � @_ ��( @` K A` ��( B` ��( H` ��( �l �` ��( �l @d ��( 8 j �� �l @j �
� @l ��( � �m �c F| �n ɚ( @o ֚( � �o �( �l �p �( � �s ��( �l t ��( � @t �w ; �t �( ; u � �l �u ��( �k �u ,�( �k �v 5�( �l �w �� �l �z �$ �l { $r( �| @�( ; �| _a @} �u Cl �} L�( _�( �l @ i�( �l �� r�( _l �� |�( �l � ��( �l �� *h � �� i~ �l � ��( �� ��( �� ��( �l �� ��( �l � ��( �l @� ��( �� ˛( �l �� ӛ( � �l �(
�' �( �l ��( �l D �( �l � �( �l � � �l � �( �l � �( �l � "�( �l 6 (�( �k < � @< �l " �l �l �l �l 5�(
P D�( \| <_ @ � �| ` 6] Z| @ J�( �l � Z�( � i�( � x�( � ��( �l @ �p \| ��( x 7 �| 6] Z| @ �g \| � T= �c � � � f � A � � ��( @ G 2 � � @ ��( � � ��( G � ��( � ʜ( ( � �l �( � @ �l �( ��(
�( � �( Z| �b
� @ "�( @ )�( ` 0�( �| � 3�( ^| � �\ ^| 6�( � @ Dq �l @ �l ?�( �� al �� �l @ l M�( p - �l �� � @ ^�( � m�( � �( � ��( � ��( "�( �l @ Q| �l ��( '� �l ��( � @ ȝ( h � ; �=
�l � �a �k � `�( E ߝ( � _a � �( �� . ��( . ( �l �( h � E � �o � �( E � �( � @ $�( 8 � �| P| � E_ �l � �( 5�( �' �l )� �l � B�( �l #k �l @ �_ �l � ��( �l � P�( � �: G P= �l @ �l �m n ��( � E_ �l @ % G � <_ � �l ��( ` E_ �l ��( � @ � @ I! @ 7j . ` ��( 8 � ʞ( 8 � Ҟ( G � ޞ( O* �l '� �l @
�l �l
�l �l �( @ �� �l
�l �l ��( 0 ` �
�( �( b( . @ �( ` '�( E E_ �l � l� �l J � @ � @ G 2 � �� u. � .�( �l 6�( P L�( �k T�( � b�( � k�( @ z�( � �Q T ��( @ ��( � ��( � ��( ( . ʟ( ן( �k( xl( , �k( , @ �( H � ��( ;
�( E � �n �l �l �l �l 2�( O�( w�( ��(
c| ��( ��( Š( ͠( �( �( �( �( "�( 2�( B�( R�( b�(
s�( ��( ��(
��( ��( š( ֡( �( ��( �( �( )�( :�(
j| K�( � ^�( x�( ��( ��( Ӣ( �( �( @ �( � 5�( N�( k�( ��( ��( £( �ܣ( �( ��( �( "�( 5�( F�( Q�( @ \�( � e�( t�( ��( ��( ��( ��( Ƥ( @ դ( � �( ��( �( $�( .�( =�( M�( @ ]�( � m�( }�( ��( ��
�| ��( 8 �& �| ��( @ �5 � ��(
Υ( �( ��( �( )�( ;�( I�( @ ]�( � o�( ��( ��( ��( �?Ϧ( ��?�( ��( �( 6�( P�( m�( y�( ��( ��( ħ( �( ��( �( �(
�| �( �P �=
'p &�( ` @ �� � }) 3 � � � @ 0�( A 7�( B �& �A � � A�( M � k�( � v�( � ��( � ��( � ��( � ��( � ( Ĩ( � 0 Ԩ( � 8 �( � @ ��( � H �( � P �( � X %�( � ` /�( � h 9�( � p D�( � x V�( � � c�( � � q�( � � ��( � � ��( � � ��( � � ��( � � ��( � � ԩ( � � �( � � �( � � �( � � �( � � /�( � � D�( � � U�( � � i�( � t�( � �( � ��( � ��( � ��( � ( ª( � 0 Ҫ( � 8 �( � @ �( � H �( � P �( � X $�( � ` .�( � h 8�( � p C�( � x U�( � � b�( � � p�( � � ��( � � ��( � � ��( � � ��( � � ��( � � ϫ( � �( � �( � �( ) ( +�( ) H E�( ) h V�( ) � g�( } � v�( � � ��( } � ��( � � ��(
� '�( � ��( � � ��( � � Ϭ( � � �( � � �( � � �( � � �( � � $�( � � 5�( � �g( } a�( � o�( � }�( � ��( � p ��( � x ��( � � ��( �
� X�( �Z ŭ( E �( � ��( � �( � �( � �( � +�( � ( F�( � 0 X�( � 8 a�( � @ g�( � H }�( � P ��( � X ��( � ` ��( � h ��( � p ��( � x �( � � ή( � � ( � � �( � � �( � � $�( � � 6�( � � E�( � � ^�( � � p�( � � ��( } � ��( � � ��( � � ��( � � ��( � � Я( � �( � ��( G
�(
@ +�(
� E�(
� R�( � l�( � ��( � ��( � ǰ( � �( � ( �( � 0 �( �~ 8 '�( } #�( � 3�( � C�( � R�( � ( a�( } 0 p�( � @ ��( � H ��( � P ��( � X ��( � ` ı( � h �( � p �( � x �(
� +�(
� :�( � I�(
� ^�(
� �i( � r�(
� �( � ��( �l ��( �l ��( @ β( �
Ӳ( � ز( � � �( ` �� � ��( � �( G_ Mn � � ��(
Wj � @ �( � H �( � � �(
%�( � ( 4�(
@ C�( ) � R�( ) � �
� '�( ) Bv
a� � ` \�( : e�( ) u�( � |�( � ( ��( � 0 ��( � 8 W } @ �z
G P ��( � � ��( � ��( � � ) ��(
@ Ƴ( � � ѳ( �
۳( � ��( � �( � .�( � R�( ) `�( � 8 �g( � @ |�( � �( � ��(
X ��( G � ��( � � )i( �l ִ( �l ��( �l �( �l 0 I�( �l @ l�( �l P ��( �l ` ��( �l p ϵ( �l � �( : � ��( �l � #�( m � 4�( �l � Y�( m � j�( � ��( � ��( � �( m � � @_ ��( � �g( � �( � � ��( � � 5�( � � 0h( � X�( m S�( �l x�( �l �|( m $ � �{ ��( ' ��( � ��( � ͷ( � ڷ( � }�( � �( � ( �( � 0 �( � 8 ,�( � @ >�( � H K�( � P Z�( � X l�( ) ` �( � � X�( � ��( � H ��( � P ��(
X ��( � � ø( �
ڸ( �
:�( m~ �(
X �( � � &�( � 7�( � � �( � E�( � � X�( �
j�( � {�( � � �l( � ��(
��( � @ ��(
X �l( � � ˹(
� �(
� 0m( m
� �( . $�( � -�( � 6�( � >�( � K�( � Z�( } ( h�( � 8 x�( � @ ��( } H ��(
X ��( } � ��( } � ˺( ) � ۺ( � � �( � � �( � � �( � � )�( � � 8�( � � I�( � � ^�( � � �� � u�( � ~�( � ��( � ��( � ��( � ( һ( � 0 �( � 8 �( � @ -�( � H I�( � P �( � X X�( � ` w�( � h ��( } p ��(
� ��( � � ͼ(
� ܼ( � � �( � � )i( �
�( � � '�(
m �( : 7�( �l G�( n�( ��( ǽ( ( � ��( � �( � t( � ( ��( � 0 �( � 8 )�( � @ ��( �l H A�( } � X�( �Z :�( � N�( ) ` V�(
� e�(
� �i( � r�( � � ��( � ��( � � ��( � ƾ( � � e�(
m (
�g( � ��( } �( ) �( � 0 �( �~ 8 '�( �
:�( � @�( � � �i( � R�( � � �( � a�( � � ��( m p�( ��( ��( ¿( �( ��( �( -�( D�( B �g( : �\ � `�( � o�( � @ ��( � H ��( � � ��(
� ��( � � �i( � � ��(
�(
@ �(
�
�(
� �(
(�( � @ =�( � H V�( � P g�(
X v�( � � ��( � � ��( � � ��(
� ��( � � ��( � � �( �
�( � 0m( �Z
�(
0�( } @
@�( � P
Y�(
X
r�( � �
�o( �Z ��( � ��( � ��( G_ ��( � � ��( m~ ��(
X ��( � � ��( �
�(
�(
@ :�(
� U�(
� z�( �
��( ��( m~ ��(
X ��( � � ��( � ��( G P �( � � �( �
0�( � @�( � � I�( �
� Y�( � i�( � ��( G_ ��( � � ��( �k ! ��( ) �! ��(
" ��( � @" L|( m # � ��( �( � (�( � 5�( m E�( 3 i ) �r( � V�( } ( g�( � 8 �g( � @ p�( � ��( � ��( � '�
X ��( � � )i(
7 � @ '�(
��( � @ ��( � ��( �
��( �
e�( � ��( ) ` ��( � � ��(
� ��( � � �(
� �( � $�( � 2�( � B�(
��( � @ Z�(
X �l( ) � n�( ) � ��( � � ��( ) � ��( � � ��( �
��( �
��( � ��( �
��( � ��( � �( } �( � (�( � ( =�(
@ M�( � h �p( G � t�( } � ��( ) � ��( ) � 7�( � ��( m 0 �l ��( �g(
��( � @ ��( @ �g(
��( � @ X�( � ��( � � ��( �( 7�( U�( u�( l @ f ) u( ) �
@ �( } � ��( � � } } � ��( � � ��( } � ��( ) � V�( } � ��( } � �r( � 2s( � ��( � ��( � ��( � Sr( � ( ��( � 0 o�( � 8 7 � @ � �
�(
�( � @ %�( ) H 1�( � h ?�( � � E�( ) � g�( � � Q�( } � \�( } � f�( � � u�( � � z�( ) � ��(
��( � @ :�(
4* � @ �i( � ��(
��( � @ ��( �l ��( �l ��( ) ��( )
�( � @ �( } X &�( � h Ys � � 2�( � � B�( � � F�( � � T�( � � d�(
� ��( �
�(
t�( � @ 0�( � ��(
��( � @ Y�( � ��(
��( � @ ��( �
! ��(
" ��( � @" L|(
# �! � @# �|(
$ ��( � @$ ��( � X$ ��( ) `$ �( � �$ �( � �$ �( � �$ �( � �$ '� G �$ �( } �$ /�( � �$ =�( � �$ N�( � �$ \�( � �$ �|( � % f�(
% r�( � @% �(
& Ah � @& ��(
' ��( � @' ��( � ( ��( �
* ��(
+ ��( � (+ ��( � @+ �}(
, ��( � @, ��( � - ��( � �- �( �
. �( �
/ �( �
0 -�( �
1 =�( � x1 A�(
�1 H�(
�1 O�( � 2 ]�( � 4 �( � 4 m�( m 4 � }�( ��( � ��( � �( } u( ) �g( ) @ � ) ` �( � � X�( ~ �l(
��( � @ 0m(
��( � @
��(
7 � @ ��( m � ��( ��( �( -�( K�( d�( ��( ��( � �g( �
��( ) ��( � ��( �l ( )i( � :�( ) ��( � ��( ) � �(
� �i( � ��(
!�( � @ ,�( � >�( � N�( � b�(
r�( � @ ��( ) ��( } ��( } 0 ��( � @ ��( %m
��( m ��( m ��( &m @ � ��( �( �( 2�( ! � u�( � \�( � B�( � D�( � V�( � o�( � ( f ) @ ��( � ` ��( � h lz( � p ��( � x �( � � \�( } � ��( ) � X�(
4* � @ )i(
��( � @ '�(
��( � @ :�( � ��( � � �i( �
�(
,j( � @ ��( � ��( � � ��( � ��( � � �l( � ��(
�( � @ G m �( ��( *m m )�( 9�( ,m m )m +m A�(
� �g( ֪ �i(
T�( � ( `�(
@ o�( � � |�( � ��( �
��( � � ��( /m -m < � ��( ��( ��( �( �( /�( � u�( � A�( � �( � O�( � S�( ) f ) @ ��( � ` D�( � h lz( � p ��( m~ x \�( } � ��( ) � X�(
4* � @ )i(
��( � @ ��(
_�( � @ :�(
n�( � @ �i(
s�( � @ �( � ��( � � ��( � ��( } 0 ��( G @ ��( } p ��( � � 0m( �
G m ��( 1 �g( ) f ) �g( � @ X�( � o�( � 8 4* � @ )i(
��( � @ ��(
��( ) @ �( � ` �( � h �( � p ��( � x ��( � � u�( � � ��( � � ��( � � /�( � � ��( m~ � :�(
H�(
@ V�( � � f�(
� �(
� �i(
�( � @ �(
7 � @ Bv
"�( ) @ a� � ` O�( � 0m(
� � (
�
@
Mn � �
��(
1�(
@ ?�(
� �
� O�( �
m�( �
��( � �
��( � �
W } �
�z
G �
�o( �
4� �
}�( � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( �
4� �
��( m ��( : @ ��( ��(
��( ) @ ��( ) ` �(
� �
� �( @ �g( �
X�( m u( � � ��( � � � � � 7�(
K# � �6 � � X�( � �( � � )i(
�( � @ '�( �
� 6m �( � 3 m S�( � K# � �6 � � X�( � �( � � n�( ) w�( ) ��( � @ '�( �
��( � �( � 3 (m ��( ��( ��( �( � K# � �6 � � X�( � �( � � 9�( ) w�( ) B�( � @ '�( �
��( � �( � 3 2m F�( K# � �6 � � X�( � �( � � )i( 3 m b�( � �
�( � @ � �
��(
�( � @ ��( �
��( � K# � �6 � � X�( � �( � � )i( 3 $m ��( � K# � �6 � � X�( � �( � � )i( 3 (m ��( � K# � �6 � � X�( � �( � � )i( �( .m �( � K# � �6 � � X�( � �( � � )i( 3 2m .�( � �
�g( � @ � �
)i(
��( � @ 4� �
J�( � K# � �6 � � X�( � �( � � e�( � m�( � |�( � @ '�( �
��( �
4� �
��( m ��( � @ ��( �
B $�( � C ��( ~ C ��( r D ��( � �
�g( � @ � �
)i(
��( � @ 4� �
��( K# � �6 � � X�( � �( � � )i( � ��( 3m iu( I ��( ��( �( $�( <�( J�( `�( x�( ��( ��( ��( ��( ��( ��( �( �( 4�( H�( a�( z�( ��( ��( & ��( ��( ��( �( �( 5�( R�( o�( ��( ��( ��( ��(
�( *�( ' H�( g�( ��( ��( ��( ��( ��( �( " 6�( $ V�( % p�( ��( ��(
��( ��( ��(
�( @�( b�( ~�( ��( ��( ! ��( & ��( �( � t� ��( , � �( 0% v� � � F% � � )�( , � 2�( ��( , 0% � � X B�( 0% v� S�( , � F% , � ]�( {�
� @ q�( {� 38 �( �
@ ��( � &� ��( ��( &� � ��( ��( � , �5 t� ��( ��( + S> + �( , X3 v� @ ��( , 0% �( + 0 F% @ �! + P � , ` ^%
� �( , � ��( , �( , 0% @ �! + P �( , ` *�( �
� 2�( , � 1 0% ?�( + W�( + n�( + 0 y�( , @ ��( , ` ��( , � �8 �
� xL% Um ��( Vm oB Wm ��( Xm ��( &� } ��( + X3 t� ��( �g( � �) �( � ��( }�( } h` 0 ��( , ��( , &� �
\m ]m �( &� � ѩ X3 ) ^m @ s3 � � �( � t� ��( , � �( 5�( �
H�( �
@ [�( &� } � + 55 , o�( �g( � ��( ��( ��( + �� + ��( �� fm aQ Sm �V Km ��( Lm ��( Mm � Om �� Pm �� Qm ��( Rm ��( Tm �� Ym ��( Zm ��( [m à _m �r( `m ��( am ��( Nm �( cm �{( dm �( bm , �( @ &� � X3 � s3 fm �9 em �5 + � `( � f � $�( ;�( R�( h�( ~�( ��( ��( ��( ��( �( !�( :�( W�( t�( ��( @ ��( ��( ��( ��( ��( �( �( +�( @�( U�( k�( ��( ��( ��( ��( ��( �( �( &�( 6�( !� F�( E_ �k U E @ � qm � �: G � �� tm rm U�( m�( �] E u � @ {�( �@ xm L� @ ` X� � vm ��( �@ xm ��( @ ��( ` ��( p ��( � ��( � ��( � ��( ��( ��( ��( ��( �( �( '�( 0 J zm 3 � E- @ Q . @ <�( \R L�( Y�( @ h�( w�( �( ��( ��( ��( ��( ��( ��( ��( �( �m $9 �m
�( �m 6s -�( �� �@ �� m @ 6� � � 6 � 5�( N�( i�( ��( ��( ��( ��( ��( �( 3�( R�( j�(
��( ��( ��(
��( �( #�( E�( a�( ��( ��( ��( ��( �( )�( K�( n�( ��( ��( � ��( $ ��( � ��( ( ��( � ��( 8 �( � �( @ .�( � B�( S�( � e�( � x�( � ; �V �m � W E �
�m �m �m ��( � ��( ��( ��( �@ @ ��( �@ � l�( �k � 3 � E- @ � @ ��( ` �V �m � -^ �m � ��( ��( �( �m @ � � ��( �m � ��( � ��( ; � �m � �6 � gm �m
�m Jm �m sm ��( �m ��( �( +�( >�( Q�( d�( ~�( ��( @ ��( � ��( ��( ��( �( 0�( I�( @ d�( � ~�( ��( ��( ��( ��( ��(
�( �( *�( =�( O�( a�( t�( ��( ��( ��( ��(
��( ��( ��(
�( �( 0�( B�( P�( ^�( l�( {�( ��( ��( ��( ��( ��( ��(
��( �( �(
.�( A�(
P�( d�( u�( ��( ��( ��( ��( ��( ��( ��( �( 4�( E�( @ V�( c�( p�( , }� , {�( , ��( , `( �5 } ��( �m �m 8! �m ��( ��( , ��( , �m @ ��( P � {m -^ �m � ��( � �( �m � @ �6 `
�m �m �m ��( p ��( �m ��( � ��( �( �( 7�( P�( f�( |�( @ ��( � ��( ��( �( !�( 9�( P�( n�( ��( ��( ��( ��( 8 �� ��( @ ��( � ��( � ��( � 1 � ��( ��( �m @ ��( � �( �m � � � �( -�( H�(
\�( r�( ��( ��( ��( ��( ��( @ �( � �( 3�( �F�( � \�( p�( @ ��( H � % P ��( � � ��( � 1 � ��( ��( ��( �( �( @�( i�( ( ��( ��( ��( @
�( ` �( � B�( � ��( � 0% � ��( ��( ��( ��(
0 �� ��( @ ��( � ��( � 4* � 1 � ��( ��( ��( @ ��( ` �( L�( Y�( � 0 $�( ;�( T�( ��( f�( �m ��( `
�m q�( �
��( ��( @ � ` ��( �
� ��( �
� ��( ��( � ��( ��( ��( �( )�( M�( w�( ��( ��( �( ��( !�( 1�( D�( ]�( ? v�( ? ��( @ ��( �( �( ��( � �( � 7�( X�( � s�( ��( ��( ��( �( �����( ���� �l �( ` � {m �( �
� �( 3 � #�( 3 4�( @ -^ �m � �6 �
�m Jm �m �m >�( W�( p�( ��( " ��( ��( �( ��( � ��( �( ? *�( �P :�( � D�( @ � � � � r� � [�( � f�( � r�( ��( ��( @ ��( ` ��( �( �| �( ; � �( � �( �m :q( � �( � �( � ��( $�( 8 �( x �( �| � �6 � �( 3�( S�( t�( ��( ��( K# � ��( �( �( �( h ;�" ym �( ; � �( � �( �m @ �( � � (�( � � � � 4�( �( @ � ` 4�( � �? � � � =�( � F�( � P�( E �m Y�( j�( ��( ��( ��( _| ��( �m ��( � 1�( � %�( � �( � ��( �( ��( @ ��( ` �a
�m � �� 3 � X� �� �m @ 4* @ �( ` 4�( � �( � wq � ��( 0
�( �| ,�( @ �6 ` �( �a
�m �� @ �� � ,�( p <�( �m ��( �m @ vs �m � L�( �P W�( [| �m �
�] wm �� �m � _" �m � \�( k�( 3] �m @ ` � � 1 � � � f � �o � �t( �m G$ � v�( � }�( � ��( � ��( ; ��( ; � ��( ; ! �� |m �! ��( �! ��( " � �| " ��( @" �( `" �m �( � � �m �( � �( � ��( � �( � �(
�( �( � � �m _" �m � vs �m � C# �m �
�( � f � 1 �m �m )�( � � �m 3] �m � vs �m � C# �m � �Q l � �( f 4�( P 3] �m _" �m @ J�( �� � @ ��( �m � �k R�( x ^�( �m ;� � � P c�( �m l�( �m z�( �m �r( �m � �l ��( @ ;�" ym ��( wm � �a
�m � *� � ��( � ��( ��( �( �( � ��( Y| �( �m �] �m
�� �m � �( � @ �( �m @ �( �m � *� � +�( ; 8�( ; � wq E�( ; @ M�( y| � �� � Z�( �m h�(
� t�( ]| z�( �m � �] wm � �� �m @ ;�" ym @ �( ;
� @
�? `
� �
�( �
�a
�m �
` � �( ��( X ��( ~| �( � f�( 8 ��( �m Y� �� � ��( @ ��( l � ��( �( �( �( .�( K�( g�( ��( ��( ��( �( �(
) 7 ) U )
� ) � ) � ) � ) ) ) ;) f) �) �) �) �) �) �) ) ) %) 7) V) h) )
�) �) �)
�) �) ) ,) J) c) z) �) �) �) �) W E f 8 @ �m �) @ �) �) ) () ?) T) r2 (� �� |m @ m) � � �
�m y) 0 J � �g �m � @ �) �) �h �J } kv 3 @ �H 3 � �) 3 � �� E �) @ �2 \} � ��( � ��
�m �) �) �) �m ) ( ^ t| n< @ �m �l �m �m |m �m wm �m {m &) �m �m �m �m �m �m �m �m �m �l �m �m �m �m D �m �l �l �m �m �| �m �l �m �m �m 0 �m �| �m �m ym c| )| � :) S) m) f ) �) ) �g( � @ �r( � �) � �) � u�( � y( � 1�( � ( Ah � @ '� G �) � 0 �( � 8 ��( � @ '�( �
�) � `�( � ��( G 4* � @ �i( �
�(
7 � @ ��( � � � � e�( � �) �
�) m �) } � ��( : ) ) 3) f ) F) ) �g( � @ �r( � �) � �) � u�( � ��( � 1�( � ( Ah � @ '� G �) } 0 ��( � @ '�( �
:�( } ��( G S) � @ �i( �
�(
7 � @ ��( � � � � e�( � ��( �
��( : b) v) �) � �g(
f ) @ ��( � ` y( � �( ~ )i( %m G m �) �) �) �) ) &) � R) ) }�( � g) � � y) � �) � � )i( � �)
f ) �) � Z�( �
( � ) � �) ) � � ) � X�(
4* � @ )i(
��( � @ '�( ֪ �) +n ��( m G m �) � K# � �( � � X�( � �( � � )i(
�) � @ '�( �
�) � K# � �( � � X�( � �( � � )i(
) � @ '�( �
!) � K# � �( � � X�( � �( � � )i(
�( � @ '�( �
<) � K# � �( � � X�( � �( � � )i(
n�( � @ '�( �
W) @ �g( �
X�( ~ ��( � � q) � K# � �6 � � X�( � �( � � �) ) w�( ) n�( � @ '�( �
� 1n �( � 3 'n �) � K# � �6 � � X�( � �( � � )i(
�) � @ '�( �
�) � K# � �6 � � X�( � �( � � )i(
) � @ '�( �
�) � K# � �6 � � X�( � �( � � )i(
�( � @ '�( �
�) � K# � �6 � � X�( � �( � � )i(
n�( � @ '�( �
) � �
�g( � @ � �
)i(
�) � @ '�( �
" ) �
K# � �6 � � X�( � �( � � )i( � > ) ,n J ) � �
�g( � @ � �
)i(
) � @ '�( �
k ) � K# � �6 � � X�( � �( � � )i( � � ) #n iu( �Z � ) � � ) ~ �u( !n ��( r D � ) � �
�g( � @ � �
)i(
�( � @ '�( �
� ) � K# � �6 � � X�( � �( � � )i( � � ) %n iu( �l ��( r D
) � �
�g( � @ � �
)i(
n�( � @ '�( �
,
) � K# � �6 � � X�( � �( � � )i( 3 'n H
) k
) � K# � �6 � � X�( � �( � � )i(
) � @ '�( � ��( � � �
) �
) �
) � K# � �6 � � X�( � �( � � )i(
�
) � @ '�( � ��( � � �
) �
) ) ) h � 1 a� @ 4�( ` ��( � � � �( � Ah � '� ��( 7 @ ��( ` 4* � ' ) � ��( �> �a
�m @ 1 ) � B ) � N ) � ^ ) � �6 �l Dn n ) ( g : ~ ) : @ � ) : � � ) : � B : � ) ( � ) � � ) � @ � ) 3 � � ) � � ) � � ) � )
� �a
�l �i �� � � @ ) T � ) � � ) � M E L� @ ( ) . ` X� � 8 ) ( �g( � E- � �( � J ) � Z ) � 0 <k( � h h ) � p v ) � x � ) � � � � �
; � � �� � � � � � � � � � ) } � �) } � � ) } � ��( ) � ��( � � )
� )i( �
� ) � � ) � � ) � � ) } � ) � ( a�( � 0
) � 8 7 � @ V� � � �
) �
�l( �Z %
) � =
) � � M
) �
�o( �~ lv( � � ��( G � g
) �
w
) �
) �
) @ �
) � �
) �
) ) ) *) @ =) O) a) s) �) �) � �) �) �) � ) /) G) @ [) � k) {) �) �) �)
�) �) �) ) &) <) Y) v) �) �) ) �) �) �) ) ') =) T) h) ! |) " �) # �) & �) ' �) % �) , �) - ) @ � ) 1 �% -) , X3 ) @ 9) , ` V� �
� � �
� B) , s3 � Q) , � �5 � � ^) � 7 ) � m) 7 � � 0 �� @ �� P �< ` x) �) �) On �) P �) Pn �) Pn � �) ;| @ �) . @ �) . H �) ` �) ) %) @ ;) ` [) � {) o� , �u , 5 �
@ �) + �) + �) 0 1 &� � �) + Tn 0 �) �
@ �) , � X3 �k � �) �) �
�) � , # , �8 �
@ �) ) &) 8) G) T) a) y) �) �) � \|( �� +a @ h ` �) �P # � Yn h @ s< � �) � @ �) Zn ` �) ]n �) @ �) �� �) gn � @ �$ � ` � � �) Zn @ ) � Ԟ � ) � ) � N � �B � E_ �l @ �� 1 � \n h - E 0) E @ <) � � E) � �+ � �� _n @ O) an � U) an � \) an c) @ m) � u) � !\ � �� Qn �) �� �) �| �) [n �a
�m � �( � dn `n J � �� X� +a an @ �) � � �) bn �) Gn �) . @ �) an � �) ; � �
@ �) [n � � ^n cn �) 0 ^ t| � q| @ n< � ) ) 0) G) Z) ( k) ; �( � DN � � v) 0 ^ t| � q| @ n< � �) � �) Un �) Nn � �) Sn � �) � Hn n In Wn Vn in Un Sn Nn �l hn en �m u| �m
?| xn �) �) ) 0) b) � �) �) �)
�) � ��( } �) � ) � 6) � ( \) � 0 �( ) 8 �)
X �( � � �)
�)
@ ��( � � )i( �l �) �) ) +) M) q) �) �) �)
�k w�( ) ) d| @ ,) ��( Vl C) E @ J) � 1�% . � �� �: y� �: P) 0 _) ; s) � 5 �n � {) H �) ; C) E � �) ; � �) ; @ �) ; � �n �l �n �n ~n
�k �) � ql �) nl � �) ) ) 5) N) c) w) �) �) �) �) �) �) ) % ) : ) G ) ] ) l ) � ) � ) � ) � ) � ) � )
�l ) ) 8 ) V ) m ) � ) � ) � ) � ) ) , )
< ) P ) h ) � ) � ) � ) � ) � ) ) ) 8 ) T ) � ) �� � ) 6 �a �k @ �k
�n �l
�n �l
�n �l
�n �k
�n �n �n �n �r , � , �r �n � ) �
�( + ��( + � ) 0 # �n � ) , @ � ) ` � ) h �n p {� ) � � ) G � Bv � � � � ) , � !� � � ) ` � ) �| JK �n @ � ) � � ) �
b^
% � % P
�l �n �n �( ( �a Z z� �
@ ) ( � � ; � ) � �=
�l ) �? @ � ; � �n 4 ) B ) O ) \ ) i ) x ) � ) � ) @ � ) � � ) � ) � ) � ) � ) !) !) *!) @!) T!) k!) 3 � �!) �
�!) �
�!) �
�!) �
�!) �
�!) �
") �
0") �
J") �
e") �
") �
�") �
�") �
�") �
�") �
#) �
.#) �
Q#) �
s#) �
�#) �
�#) �
�#) �
�#) �
$$) �
J$) �
q$) �
�$) �
�$) �
�$) �
%) �
1%) �
N%) �
j%) �
�%) �
! �%) �
" �%) �
# �%) �
$ &) �
% #&) �
& G&) �
' j&) �
( �&) �
) �&) �
* �&) �
+ �&) �
, ') �
- ?') �
. c') �
/ � �
0 �') �
1 �') I 2 �') � �!) �
�!) �
�') �
�') �
() �
() �
6() �
N() �
e() �
�() �
�() �
�() �
�() �
�() �
)) �
4)) �
7�( �n � Q)) @ })) � �))
� �))
� �)) � �)) � � �)) � *) � � "*)
>*)
@ �(
� Y*)
� :�( � m*) � � �i( : {*) �
�*) � �g( �n �*) �
�*) �
�*) �
�*) �
+) �
+) �
-+) �
@+) �
Y�( : R+) �
$ n+) �
% �+) �
& �+) �
' �+) �
( �+) �
) �+) �
* ,) �
+ �}( �n , @ 2,) � `,) �
t,) �
�,) �
�,) �
:�( �n @ �,) � �,) �
-) �
-) �
&-) �
:�( �n 8-) � c-) �
r-) �
)i( �-) �
�-) �
�-) �
�-) �
��( �-) �
�-) �
�-) �
�-) �
�-) �
.) �
.) �
-.) �
:.) �
Q.) �
g.) �
�.) �
�.) �
�.) �
�.) �
�.) �
! /) �
" -/) �
# �|( �n $ @ U/)
� �/) �
�/) �
)i( ~ �/) �
�/) �
�/) �
�/) �
0) �
+0) �
7�( �n D0) ! � q0) �
�0) �
�0) �
�0) �
�0) �
1) �
01) �
Y1) �
�1) �
�1) �
�1) �
�1) �
2) �
(2) �
F2) �
j2) �
�2) �
�2) �
�2) �
3) �
+3) �
J3) �
h3) �
�3) �
�3) �
�3) �
�3) �
4) �
=4) �
V4) �
n4) �
�4) �
Y�( �n � �4) + � �4) �
�4) �
5) �
5) �
65) �
L5) �
a5) �
�5) �
�5) �
�5) �
�5) �
6) �
"6) �
B6) �
a6) �
�6) �
�6) �
�6) �
�6) �
�6) �
7) �
7) �
;7) �
Y7) �
v7) �
�7) �
�7) �
�7) �
8) �
&8) �
I8) �
n8) �
�8) �
�8) �
! �8) �
" 9) �
# (9) �
$ N9) �
% s9) �
& �9) �
' �9) �
( �9) �
) :) m * :) � H:) �
Z:) �
k:) �
�:) �
�:) �
�:) �
�:) �
�:) �
�:) �
�:) �
;) �
&;) �
8;) �
O;) �
e;) �
z;) �
�;) �
�;) �
�;) �
�;) �
�;) �
<) �
<) �
4<) �
N<) �
i<) �
�<) �n � �<) ' � �<) �
�<) �
�<) �
=) �
-=) �
P=) �
r=) �
�=) �
�=) �
�=) �
�=) �
�=) �
>) �
0>) �
R>) �
u>) �
�>) �
�>) �
�>) �
?) �
%?) �
C?) �
`?) �
�?) �
�?) �
�?) �
�?) �
�?) �
@) �
E@) �
j@) �
�@) �
�@) �
�@) �
! �@) �
" A) �
# AA) �
$ jA) �
% �( �n & �A)
� �A) �n �A) �n �A) �n B) �n <B) �n _B) �n |B) �n �B) �n �B) �n �B) �n C) �n C) �n �g( �l 2C) JC)
��
@ OC) } � TC)
� ٣ G � =� � �( �- cC) ) � mC) � � ��
� l �n |C) �C) �C) �C) �C) D) AD) bD) �D) �D) �D) �D) E) ! B JE) � XE) � fE) @ tE) @ �E)
@ �E) @ �E) @ �E) @ �E) !@ �E) "@ �E) #@ �E) $@ F) .@ %F) P 3F) P AF) P OF) P ]F) P kF) P zF) P �F) P �F) P �F) P �F) P �F) P �F) P �F) AP �F) 1P �F) P G) #P G) P #G) ` 6G) p OG) � ^G)
� lG) � zG) (� �G) +� �G) -� �G) @� �G) A� �G) B� �G) C� �G) P� �G) Q�
H) S� H) T� ,H) U� ;H) V� JH) Y� XH) `� fH) a� tH) b� �H) c� �H) � �H) U� �H) V� �H) b� �H) �� �H) �� �H) �� �H) � I) � I)
� -I) � ;I) � RI) H �Q( �Q( eI) + uI) , �I) � @ �I) , � �I) + � �I) + � �I) , �I) , �I) � @ �I) , � �I) + � �I) + � J) ,
J) , J) 4J) ?J) RJ) cJ) wJ) �J) @ �J) � �J) �J) �J) �J)
K) ,K) @ HK) � ^K) mK) �K) �K) �K) �K) �K) @ �K) � L) *L) AL) aL) �L) �L) �L) @�L) �M) &M) @M) \M) mM) �M) �M) �M) �M) �M) N) �Q( �Q( �Q( -O � + N) 0 (N) 8 �� �
@ � + � l� + � �Q( , � ��( �
� 0N) + 8N) + � �k �9 � @N) � MN) � YN) , � mN) yN) + })) + �)) 0 �)) 8 �)) + @ �N) + P �)) + ` *) + p "*) � >*) � 0% � Y*) � F% + � �N) + � �N) , � �N) , � �N) , �N) , {*) , @ �N) H � mN) yN) + 0% , �N) �
@ �N) �
� �N) �
� �N) �
O) �
@ O) �
� 8O) �
� TO) �
oO) �O)
�n �n �n �O) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( �
�i( �
��( m ��( : @ �O) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( �
�i( �
��( m ��( : @ �O) � �
�g( � @ � �
)i( �
4� �
�O) � �
�g( � @ � �
)i( �
4� �
P) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( �
4� �
��( m ��( : @ +P) � �
�g( � @ � �
)i( �
4� �
IP) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( �
4� �
��( m ��( : @ fP) � K# � �( � � X�( � �( � � e�( � m�( � ��( � @ '�( �
�P) � K# � �( � � X�( � �( � � )i(
��( � @ '�( �
�P) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
�P) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
�P) � �
�g( � @ � �
)i( �
4� �
�P) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( �
4� �
��( m ��( : @ Q) � �
�g( � @ � �
)i( �
4� �
'Q) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
��( �
4� �
��( m ��( : @ EQ) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
`Q) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
|Q) � K# � �6 � � X�( � �( � � )i(
B�( � @ '�( �
�Q) � K# � �( � � X�( � �( � � )i( �
'�( � �Q) � � �Q) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
�Q) � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
R) � �
�g( � @ � �
)i(
��( � @ '�( �
'R) ;� � >� � @ kv � �H � �l �n 1R) � ?R) MR) ^R) pR) R) �R) �R) �
�l �R) P �& �| �R) �| @ � E � k � #� � ��( �R) Mn @ <_ `
�n �R) 8 �& �| ӽ �| @ # � �Q �
�n �R) �R) S) (S) AS) ]S) xS) �S) � �S) � �S) �S) �S) �S) T) @ #T) � 4T) @ JT) aT) yT) @ �T) � �T) �T) �T) �T) @ �T) � �1 } Kx .� + �n � + D + U) �n Y �n 8! , U) .U) BU) VU) jU) ~U) �U) ( #� + 0 �U) , @ �n ` �U) ) , �5 � �U) 0 JK �n �U) K �
�5 , @ � ` �U) �U) , � + � + 0 �U) , @ �< , ` V) &� ) `( X3 m~ ( V) o� , �9 oS (V) 6V) CV) QV) ^V) + jV) + uV) , �[ @ �V) H �5 � P �V) h �V) + p �V) �V) �V) �V) �V) �V) �V) W) \ o T*
o �" , W) , @ #W) , ` -W) :W) , NW) , \W) , @ fW) , ` pW) @ �� o �F o � yW) o W) o � �W) �W) , # , �8 �
@ �W) { + �W) + # , �8 �
@ �W) �W) , �] , �W) , @ �5 ` �7 + p �W) &� � o �
o o o �m o 8| �n o
o o o o o o o o o �n o �n �n Jv � X�( �l ��( sl @ Ԟ � . � �W) X) "X) <X)
�|
�|
} XX) oX) �X) �X) �X) �X) �X) �X) �X) Y) Y) *Y)
=Y) WY) hY)
�Y) �Y) �Y) �Y) 0
3 �� 3 @ �Y) 3 � �Y) 3 � l9 /o �� 0o @ �| �| �Y) h �g �| '� 2o .o Z) %Z) MZ) rZ) �Z) �Z) �Z) [) )[) R[) o[) �[) �[) �[) \) 0\) V\) y\) �\) �\) �\) ]) =]) � R]) :o � _]) q]) �]) �]) �]) �]) �]) %^) I^)
c^) �^) �^) �^) �^)
_) 7_) T_) _) �_) �_) �_) `) `) 8`) h`) �`) �`) �`) 'a) Qa) �a) �a) �a) b) 6b) Sb) wb) �b) �b) �b) c) 4c) rc) �c) �c) ,d) � �g( �Z �� �
Fd) � �� : `d) � �d) �
�d) �
�d) �
�d) �
�d) � �d) Fo �d) Eo �d) Do �g( : e) 'e) �
2e) � � � � <e) �
Ge) � Qe) � � \e) � � fe) � � �X
pe) G @ xe) } p e) � � �e) � � u� � � �e) ) � \�
� � �e) � �e) � � �e) } �e) G_ �e) ) � �e) ) � �e)
� ��( � �e) � � �e) Go
f) Go f) �� � �
� 4f) Jf) Io # �
Pf) ' qf) � ��( � f) � �f) � D�( ) �f) � @ �f) � �3 � � �( � ��( � �( � �( � � �( � � �( � � �f) � �f) � �f) � g) � g) � .g) � � �� Jo ;g) � ��(
� Eg) � Pg) G � �( � � _g) � � ��( � jg) � ` e�( � �g) � ` �l( � �g) G P �g) � � 0m(
��( � @
�g) �
v�( �
m�( �Z
�g) F�
� �g) � � �g) � � ,�
� �g) V�( Lo E�( Lo +�( Lo �( Lo ��( �
��( �
Ϭ( �
�( �
�( �
�( �
�( �
$�( �
h) �
m�(
*h)
@
:h)
�
Ih)
�
�o( � Yh) {h) �
�h) �
�h) �
�h) �
:�(
�h) � @ �h)
�h)
@ j( � � i) �
i) �
/i)
9i)
@ Ci)
� Oi)
� ϫ( �
[i) �
ei)
si)
@ ?�( � � �i) �
�i) �
�i) �
g
) �
�i) �i) �
�i) �
�i) �
j) �
.j) �
Hj) �
_j) �
yj) �
e�( ~ �j) �j) �
�j) �
�j) �
�j) �
�j) �
�j) �
k) �
k) �
e�( ~ &k) � Kk)
�g(
@ ak) � h tk) � p ��( � x �k) � � ��( � � �k) � � 0h( } � �k) � � �k) � � �k) � � �) } � l) � � l) � � /l) � � Gl) � � X�( m Vl) �l xl) �l �l) �l 0 ��( Ro @ �l) �l � �l) �l � m) �n � m) � � =m) � � hm) � � �m) � � �m) So � g �m) �m) Ho �m) Ko �m) Ho n) Mo 0 n) No @ +n) Oo P =n) Po ` ��( 8 p On) nn) �n) �n) �n) �n) o) @ 6o) � Xo) {o) �o) �o) �o) p) @ 9p) `p) � ��( } mp)
�g( � @ {p) `p) � �p) ~ � Vo �� Wo �p) � K# � �6 � � �p) � � � � 55 �
�W Xo �p) �p) q) 5q) Xq) {q) �q) �q) �q) $r) Ir) pr)
�r) �r) �r) s) 9s) Ws) us)
K# � �( � � X�( � �( � � �s) � m�( �
�s) � � '�( �
�s)
S) � @ �i(
� � @ �( %m �s) � K# � �( � � X�( � �( � � �s) �
'�( �
�s) K# � �( � � X�( � �( � � �s) � m�( �
�s) � � '�( �
�s)
S) ) @ �
) ` V�( � � �i(
� � @ t) � ��( ~ 9t) �
e�( �
Jt) �
0m( �
Yt) � �
��( : g
) � jt)
� �t) To �t) Zo � �t) �t) �t) �t) u)
l /u) Ju) ju) �u) �u) �u) �u) v) :v) ]v) �v) �v)
�v) �v) w) 7w) \w) w) �w) �w) �w) �w) x) #x) Bx) 1 o| �k) @ Tx) jt) �t) rZ �� rZ cx) eo
fo px) �x) �� !i( �x) ko @ 1 � �x) jo �x) �k �x) �k @ �� ho � ?� �
� �x) �x) �� �k � al Y� io �1 lo �x) �x) ( � ao mo @ y) y) 0y) ( � Ey) �5 @ 1 ` �6 � My) �k � �> oo Uy) _y) jy) ty) qo y) o�( � ��( ( ro @ �y) �y) � � �y) �y) �y) � 55 �y) P �? �y) yo @ �x) ko � � vo � 1 �� zo l9 �| � �� l � z) so z) xo to z) � 5z) =z) ( 3 @ �9 E � Ez) Yz) oz) �v 6 �z) �z) ^~ @ � ` �z) �z) � �9 �o @ ~o �z) �z) {) 6{) P � ; K{) �| � � �o @ �� l � R{) �| � E_ �l ]{) �o @ �l j{) � {) 9o �{) nw ;o �k �m @ � ` �a �k � �g 8 � jt) � �o �{) �{) �o E_ �l @ �g 8 � �{) 3 �o @ �{) �o �y) yo �x) ko E_ �l � @ �o � �{) �o �{) �o �{) 0 |) �| �o � |) $|) al >� ; @ 1 � 2|) H|) ^|) ` p|) �| � �o � �Y) � $|) al ނ �o @ x|) � ^~ � �z) �o � �|) �
'p �o �o �o }o � ��( [n �|) �m �|) �m �|) �|) ( [} �l 55 @ �|) � �|) �
� 1 � �o � �|) ; � �|) �|) }) =}) ]}) m}) {}) �}) �}) �}) �}) �}) l
�o �l
�o �l
�o �l
�o �k
�o `o o ,o {o po go wo no �o �o �o �o �m eo fo @ �}) �| �}) �| � �o +o no �o �l �| �| �| *o 1o �l
�o E_ �l �{) �o �}) �o � �o ��( �� �o ~) �o
�o E_ �l �{) �o � �o ~) �o cx) �o $~) �o ��& E kv -~) 5~) �o
�o E_ �l x �k �m K~) . Q~) �o
�� E a~) �n �� 3 3 n~) �o
�~) (� �: �~) �o
E_ �l �R) �n �~) K} �~) �o
E_ �l �g �m �~) �~) �o
. �~) �o �~) �o
�g �| � �k /1 �k �~) �o
/1 �k ~) �o _� ) �g �l 1 � ) �o
�o E_ �l �}) �} $) �o ,) �o
�t) � ;) �o
�g �m �& } '� ln �W " P�( " �� U) �o
E_ �l �g �m �& } '� ln �W " P�( " �� � f) �� o k) k�( u) �o
E_ �l �g �m �& } '� ln �W " P�( " �� � f) A k�( �) �o
�� �n kv �H �) �o
E_ �l �) �) � �) } �) } �) � �) E �) �o
E_ �l �) �o
E_ �l �r( �m ;� � kv >� � �H �) �o
E_ �l ;� � kv _" �m �) �o
E_ �l ;� � kv 3] �m 0�) �o
E_ �l �r( �m >� � �H L�) �o
E_ �l �r( �m `�) �o
E_ �l �g �m v�) �o
E_ �l _" �m ��) �o
E_ �l 3] �m ��) �o
� �m ŀ) �o
E_ �l K# ��( ��( E �g �m 4� � ׀) �o
E_ �l �g �m >� � �H e�( . �) �o
�m E_ �l ��) �) zm �) �o
J �m "�) �o
E_ �l 4�) A�) �o
E_ �l �( � Z�) p
E_ �l �( o�) p ��) � ��) �
�=
�l ) ( ʁ) p
�=
�l �) p ��) �� �) � +�) �
�� o E�) o K�) p
�m �� �n ]�) a�) p
� ) �| �~) K} �J } n�) p
�} �g \| �}) �} �J } �z) p
־& �} ��) p
�? �| ��) p
E_ �l <_ ��) �o � �m ��) p ˂) �o
E_ �l �) p
E_ �l ��) �o � �m ��) p
/1 �k
�) !p 8�) !p x�) !p ��) !p �) !p
W�( \| �& } #�) } ��& . *�) 'p
W�( \| �& } #�) } ��& . <�) )p
�=
'p N�) <_ �) } �) } ;� �k >� �k X�) � e�) � x�) +p
� ) �| 7j k| ��) -p
. �a 'p ��) /p ��) p
E_ �l �g �m ;� � kv >� � ʄ) 2p
E_ �l � ݄) 4p
�=
'p � 6 x< �| ��) 6p
�=
'p Wc � �) 8p
E_ �l +R ( +�) :p
E_ �l 5R �> H�) <p
�=
'p � 6 � � e�) >p
�=
'p � � (} }�) @p
�=
'p ��) �n ��) Bp
�=
'p _a �> Å) Dp
�=
'p � � �) Fp
�) �| �u �| �) o �u �) Hp
�{) �o �) Jp
�g �m �W " '� ln �� � P�( " f) p�( , >�) . I . L�) Lp
�g �m '� n �W E P�( E �� �m f) A \�) h�) Np
3] �m P�( " �W " y�) � � � 1 3 ��) Pp
�g �m f) '� n ��) Rp
G �m f) �g Z| ��) Tp
E_ �k K# ��( ��( ��( E �� �n �6 4� ��) Vp
ˆ) �o ӆ) . �? �o ݆) Xp
E_ �l <_ �) �k ��) �k �) Zp
E_ �k <_ �) >� E .� 3 �F . �) \p
�o E_ �l ~) �o cx) �o $~) �o � al ��& E kv _� ) �) ^p
�2 k| Hi E -�) `p
� D � �9 E B�) bp
�g �m �& } xL% " y�) P�( " U�) dp
^; "o �& } f�) fp
�& } �g �m �W " P�( " w�) hp
��) } �g �m �W " P�( " ��) jp
��) E ��) E )� � ��) lp
�g �m �& o �W " P�( " ��) . ) np
��) } �) �| �u �| �g �m �W " P�( " ͇) pp
��) E ��) E )� � �) rp �) �o
E_ �l �{) �o �k �m �) up
�{) �o �) wp @ � D�) �g( ֪ m�) �
�( �w ��) G � Pg) ) � ��) � � ��) � � ��( m ��) �g( �Z '�( ) ш) � �) � ( �) � @
�) }p H :�( �
� �
�� �
� �
� �
"� �
.� �
;� �
B� �
R� �
�o( zp �) �
5�) �
?�) �
K�) �
3v( �
f�) �
�x( ~p � z�) �g( : :�( � ��) � � _i( � � ��) G � �i( �p ` Ɖ) �g( : ܡ �
� �
�� �
� �
� �
"� �
.� �
;� �
B� �
R� �
�o( yp �) �) �
)�) N�) �
e�) ��) �
��) ̊) �p �) |p �) {p �) p �g( � 7�) d�) �p N�) �p �) �p �g( �
}�) K# � �( � � X�( � �( � � )i( �k �( ) � ��) �p :�( : ��) �p ċ) ۋ) �) �) �l �) -�) =�) R�) d�) v�) ��) ��) ��) ��) ) Ҍ) �) @ ��) �) �
4�) V�) �
j�) ( � ) }�( } �( � 0 |�) � 8 ��( � @ > � X ��( � ` ��) � h ��) � p � } x ��) � � ��) } � � ) � �) G � ��) } � X�( �
)i( � '� G � f�( G � '�( � ֍)
��( � @ :�( ) �) � �) � � ��) �
�( � ��(
�) � @ ��( �
e�(
�) � @ �l(
1�) � @ 0m(
D�) � @
��(
U�) � @ ��( � ��( � f�) V�) �p �) �p �g( �
��)
� K# � �6 � � X�( � �( � � )i(
��( � @ ��) �p �g �p iu( �Z �) � � ) ~ �u( !n ��( r D �)
� K# � �6 � � X�( � �( � � )i( � �g �p iu( �Z �) � � ) �p ��( r D �
�) @ &� �
�( , X3 �w �) � � � *�) , � ;�) + � `( � G�) � N�) �� b�) + j�) , � {� �j �- T% �2 v�) + �u , ��) �p �u( �p �" , ��) , � , ��) , `( ��) ��) @ ȏ) &� ޏ) + �p �) , ` ��) � �) � �O } � �) + � ?n + � �) , � �) � +�) � � + � �( , �p :�) ) @ A�) , ` J�) , � V�) , � b�) , � ;�) + � �p � G�) � o�) ��) ��) Ԑ) ސ) �) �) @ &� � �) , � �) , � '�) , � 7�) , � � + E�) } ��( , L�) �
@ W�)
� ��( , � ^�) } � `( � G�) �
e�) ��) ��) ˑ) �) �) '�) J�) q�) ��) ��) ߒ) �) " (�) <�) I�) ^�) q�) ��) ��) ��) Ó)
ԓ) �) ��) �) )�) G�) c�) q�) ��) ��) ��) ��) ٔ) ��) �) 4�) L�) q�) ��) ��) �� ��( @ *� � ��) � ϕ) � 1 � �) � {� � 0% � �) �� *� @ {� P 0% ` �) �) .�) G�) _�) ��) X �g w| � ; @ ��) ��) ��) �l
�p �k
�p �p �p �m �p �p ;| ݖ) �) �) �) 9�) � ��( ~ X�( m~ ?�)
X ��(
� X�)
� u�) � ��) �
��) �
��) � e�(
Ɨ)
@ ��( } � �) G � �)
� �)
��( � @ 9�)
� _�) �
��( � ��) � ��) �
��( �
��) � iu( !n �) �) "�) K# � �6 � � X�( � �( � � )i( �
'�( � @�)
� U�) � �( %m f�)
K# � �( � � X�( � �( � � ��( �
)i( � ��)
� ��) � @ �
��) �
��) K# � �( � � X�( � �( � � )i( � U�) � ��) �
��( �
י) �) �) !�) H�) b�) w�) ��) ��) �) �) 5�) F�) `�) ��) ��) ��) ě) ڛ) �)
�) �) ;�) S�) p�) ��) ��) �) �) +�) L�) t�) ��) ��) ӝ) ��) !�) @�) V�) @ k�) }�) ��) ��) Ğ) ݞ) ��) @
�) } �) @ � � "�) � +�) 8 6�) �| � O� @ 3 � ;�) X O�) �p V�) �u �p @ �] � ^�) � � �p O�) �p � % � � o�) � @ �M @ ��# 3 � �p {�) @ � �p 55 � �p �p �p �p ��( �X ^ t| �g w| @ {G . � ��) ��) ��) ן) �)
�) *�) J�) Y�) f�) P ��) }�) . ( . ( ��) . 0 R �k @ �e �p `
M
P| � ��) � _a � ��( 5R @ ��) � ��) � ��) � ʠ) � �� � _e � ;e � Pe 4e Je ٠) 0 �) @ �) . P ��( X �p �) $�) 8�) L�) [�) k�) �) ��) ��) ��) ס) �) �) �) -�) A�) Y�) q�) ��) ��) ��) Ϣ) @ �) � �) �) <�) U�) n�) ��) @ ��) ��) ã) ѣ) �) � �) (�) =�) S�) s�) ��) ��) @ Ĥ) � ߤ) ��)
�) �) 4�) I�) Y�) n�) ��) @ ��) � ��) ��) ץ) �) ��) �) ,�) @�) U�) i�) �) ��) ��) ��) ̦) �) �) �) K�) f�) ��) ��) ��) ç) ϧ) ۧ) �) �) �) +�)
a| F�) S�) `�) n�) ( {�) ��) ��) ��) ��) Ǩ) ب) �) �) � "�) � 9�) � L�) f�)
� q�)
� ��) � ��( � � ��)
� mC) � � ��)
� ��) � ѩ)
�) � @ �i( �
�( �- ��) � � �) � � .�) m~ � ��( �
=�) �
S�) �
i�) �
�) �
��) �
��) �
�o( yp ��) ۪) �) ` �) � K# � �6 � � X�( � �( � � )i( �
)�) � 3�) � �( � � ) m C�) Jn iu( : Y�) �
3v( �p z�) r D ��) � �
�g( � @ � �
)i(
7 � @ '�( �
��) � K# � �6 � � X�( � �( � � )i( � ��) �g( � ҫ) � �) � R�(
��
@ �(
� cC) ) � ��( � � �) � � ��) ) ��( � �) � � �) �
/�) �
D�) � ]�) � � q�) �
��) �
��) � ��) � � ��) �
ˬ) �
ڬ) �
�) � �
��( �k M� ) � ��) �
m�( �Z
�) � +�) C�) k�) ��) ��) �) �) 0�) U�) r�) ��) ��) Ԯ) �) ��) �) ,�) C�) Z�) u�) ��) ��) ��) � ȯ) � �) � �) �) �) ,�) D�) V�) h�) z�) ��) ��) ��) ��) Ұ) �)
�) �) �) )�) ;�) N�) a�) t�) ��) ��) ��) ��) ʱ) ۱) �) ��) �) (�) <�) M�) d�) s�) ��) ��) Dz) �) �) /�)
P�) o�) ��)
��) γ) �) �) ,�) <�) O�) b�) u�) ��) ��) ��) ��) �� δ) �� �) �) �) *�) I�) h�) �" )� y�) ��) ��) ��) ̵) �) ��( D�( 1 @ ��( ` �) � {� � 0% � F% � �( � �) 3�) f�) ��) ��) �) �) C�) [�) ��) ��) H ��) ʷ) ַ) @ �� ` �) � �) � ��) � �o � �) � Jq �) ��( �
@ :q( ` 0�) h >�) p M�) x a�) � w�) � ��) � ��( �k( ��) ��) ��) B` Ÿ) \�( p�( @ � " H ָ) �) �) �) %�) >�) V�) h�) B` @ z�) ` � � h ��) ��) ��) ��) ɹ) �) ��) �) '�) ?�) B` S�) l�) ��) ��) @ Ժ) ` B` � � � ��) �) %�) 9�) V�) ��) ��) ۻ) �) )�) A�) a�) �) ��) ü) �) p ��( �
�) �p @ �c q � �) q �) q @ *�) � 1 � N�) q ^�) q @ o�) ��) q � 0 ��) �p @ ��) ��) Ƚ) �) ��) �) 1�) M�) k�) ��) ��) ��) ̾) �) ��) �) /�) Q�) x�) ��) ¿) �) �) �) 9�) X�) p�) ��) ��) �) �) #�) A�) e�) }�) ��) ��) �) �) �) E�) _�) � w�) ��) � ��) @ ��) ��) p ��) �| �) [n ��) d E_ �l '� �l ��) 8 J � q Mm . @ -^ ` %� E � �) +�) H�) e�) ��) @ �c � ��) ��) ��) ��) ��) ��) ��) �) �) �) ,�) ;�) J�) Y�) h�) w�) �l
#q �k
%q �
'q �p �l �l �l q �l �p �p q P| �} ��) ��) ��) ��) ��) ��) ��)
�)
�� �a
�l =� X � G � � �) � CM � @ %�) � 5�) � M E � @ �
A B�) � �
�g( � @ � �
)i(
`�) � @ '�( �
k�) v�) ��) ��) ��) ;q <q
=q >q ��) 3 ?q l� :q @ K# � �( � >� E � _l ��) ��) �) ��( +�) 0% ( F% 0 4�) ��( Cq � ; � � @ ;� Eq >� L1 D�) p Dq � >q " �� ]n # ��( @# \�) Iq
�| 6q �l q ��( �
�l Bq Fq [n o�) &� } ��) + `( X3 m~ ( ��) ��) �� ��( @ 1 � {� � ��( � 0% � ��) �( � Rq Tq ��) ��) �) "�) [ \q n� ^q @ 7�) `q � -^ bq �
Yq
�k �l [q
�l ]q
E �l _q
l �l Xq E aq Zq E�) \�) y�) ��) ��) ��) ��) ��) �) 7�) X�) p�) ��) ��) ��) ��) #�) Q�) �) ��) ��) ( 1 Y� @ ��) P ��) ` &� p �) � �) � ��) �p 2�) P�) � �(
� \�)
� X�( G_ �Z } p ��(
� �( � � �( � � �( � � mC) ) � n�) � � �s( � � �� � � ʚ
� � )i( lq q�) G � ~�) �
:�( I ��) ��)
��) � @ ��) �
��) � m�(
��) } 0 �( G @ ��) } p C�( � � '�( �
�) �
�) �
'�) �
2�) �
e�( : @�) kq ��(
K�) � @ Z�) � r�) � � ��) �
0�( � ��) � � ��) � ��) � " ��) � $ ��) �
& �) �
' 0}( �n ( �) B�) l�) ��) ��) ��) ��)
�) % 1�) �Y � ]�) � p- � k- � �� � e�) � ( Z ) lq 0 q�) ' � �g( � ��)
�g( � @ ��)
X �( � � ��)
� �) � � ��)
� ��) � ��) � �) � �)
i( � @ 1�)
X ��( � � C�)
� mC) � � ]�)
� )i( m~ o�)
X C�( � � ��)
� ��( � � ��)
� '�( � ��) � � ��) : ��) � ��) � � ��) �
0m( �l
��)
�
��( � �)
� ��( � +�) � � >�) �
Z�) � n�) ~ ~�) �g( m ��) � � ��( } � X�( � ��) � ��) �
��) � � :�( m ��) �) � �) � )�) � <�) � \�) � Z�( � ( y�) � 0 ��) � 8 ��) � @ ��) � H ��) �
P ��) � � ��( � � ��) � � �) � � ��) � � %�) � � @�) � � [�) � m�) � �) � �)
�( � @ ��(
X ��) G � ��( � � )i( m~ ��)
X ��) � � '�( sq � ��) ��) � ��) � �( � ��) � H ��) hS P X�( } �) � �) m )i( �l #�) �g( � � m�( ) @�) � ( �) lq 0 '�( �
�_ oq �_ oq �_ oq �_ oq N�) oq �l( zp Z�) p�) uq ��) uq Y�( 8 ��) � 0 ��) ~ 0 -�( m 1 ��) ��) � ��) �
�) � �) � }�( �k X�( xq � 2�)
J�) � ]�) � r�) � |�) � ��) � ��) � ( ��) � 0 �( ) 8 �)
X �( � � &�)
G�)
@ ��( zq � � h�) �g( � ��) � ��) � ��) � ( Z ) lq 0 X�( � ��)
i( � @ ��)
X ��( � � )i( �
'�( � ��)
_�( � @ ��)
X ��) � � :�( m �) � #�) �k /�) m =�) vq E�) m Q�) m Z�) m �) �l ��) Qo ��) pq ��) qq ��) rq Bt( m ��) m ��) tq ��) mq ��) wq ��) �p �) �p �) |n )�) {q 4�) yq �g( }q � >�) �� �
�g( � @ � �
)i( � = |q ^�) � K# � �( � � X�( � �( � � }�) � ��) � �( G_ �� � � '�( �
��) � K# � �( � � X�( � �( � � �s) � m�( �
�s) � � '�( �
��) ��) ��) �l
�q jq
�� ]n ��) �q
E_ �l �� �l �) �q
�| 7 �| - g| �) )�) 9�) �q
6] �m ]�) �g �m L�) �q
�) �| _�) �q
E_ �l �� �l �� r�) �q
7 �| ӽ an h �+ X� �� ;� � kv ��) �q
an E_ �l �� ]n +a ��) �q
�� ]n �� ��) �q
an 7 �| �a
�m �� +a �� ��) �q
�p �8 �m ��) �q ��) LJ
. E_ �l ��) ��) �) �q
E_ �l �� ]n +�) �q
6] �m 6�) �q
E_ �l �J } 6] �m )( G�) � *� 6 kv /1 �k K�) �q
l E_ �l 3] �m � Z�) �q
\| � �l t�) �q
� �S =q ��) �q
�| 7 �| �a
�m �� +a ��) �q
E_ �l �g �m ;� Fn �� ��) �q
7 �| �g �m ;� Fn �J } �� ��) �q
E_ �l �S �m ��) �q ��) ɲ ��) ��
5 � } �] 3 � � �) �q �) y� /�) ɲ
�a �k Y� m �q G�) �q [�) LJ
��( �m i�) �q
�=
'p ~ ( i �q
5 � X� ~�) �q ��) ��
�=
'p <_ f 2q ��) �q
E 6] �m 1 ��) �q
E_ �l +a ��) �q
�| 3 �| �2 �} /1 �k ��) �q
�| 3 �| �2 �} /1 �k � ��) �q
�g �| ^ �p �g �m ��) �q
6] Z| �g �| �) �q $�) LJ 2�) LJ >�) �� H�) �� S�) �q
]n E_ �l �) Zn _�) �q
7 �| ӽ an �) )�) ;� � kv z�) �q
�a 'p ӽ an h �+ ��) �q
�u Dl 5 �
}) �j ��) �q
�u Dl 5 }) ��) �q
�u Dl 5 r2 ��) �q
ӽ an ��) �q
�� E � �) �q
+ E_ �n �2 d| �) �q
�=
'p 8�) �q
�2 d| �S " U�) �q
��( �m �& $o �g �| e�) �q
'p 'p � &| �$ ��) �q
7 �| F <| 1 �� �| �# /1 �k ��) �q
�| �=
'p �S �| �2 �} /1 �k ��) �q
�| 7 �| - g| �) ��) �q
�| 7 �| �) )�) ��) �q
��) �} �J } �) �q
�( �| �J } ��) �q
an 7 �| �) )�) �+ �� ��) �q
* �| �J } �) �q
��( Z| 1 y| �) �q
. �=
�l '� �l .�) r
�) �| \ F�) �} P�) r h�) �
E_ �l <_ x�) r ��) �o
6] �m ��( �g �m ��) r
6] �m ��) �m ��) r
�( �m � Jm ��)
r
��( Z| �2 f} /1 �k ��) r
7 �| ��( �m �2 \} ��) r
E_ �l ��( Qq ;� � kv ��) r
�h ^| �~) R} �J } ��) r
�=
�l E_ �l �) r ,�) p E�) p
6�) �| /1 �k `�) r
s�) �} v�) r
7 �| �J } ��) r
E_ �l �( �6 ��) !r
��) �| ��) #r ��) �q
��) 'p ��) &r
�) �| �J } �) (r
�R) �| 1 �) *r
6] Z| �J } 0�) ,r
��( �m C�) .r
�g ^| �J } W�) 0r k�) �o ��) p ��) p ��) p
E_ �l �~ . �g . ��) 6r ��) #r
E_ �l O�) �p ��) 9r �) ��
E_ �l �~ . �g . ,�) <r
� D -^ %� E >�) >r L�) >r
�g �m �( e�) Ar z�) �o
��( Z| �g �| ��) Dr
��( Z| ��) Fr
�| 7 �|
� ��) Hr
�l '� �l ��) Jr
�k �=
�l ��) �( � ��) Lr
� ��( l ��(
�) Nr
�a 'p �� � m � $�) Pr
�a 'p �� � 5R � ��( � :�) Rr
�a 'p �� � / � N�) Tr
�g \| �2 _} c�) m�) Vr
� �l ��) Xr
�g \| �& } #�) } ��) Zr
�g \| �& } #�) } ��) \r
�g \| ��) _} ��) ��) \} ��) ^r
��( �m �& $o ��) `r �) � +�) p I�) !p w�) !p ��) !p ��) !p �) !p +�) !p X�) !p ��) � ��) r ��) p
�) �| $ � �& ��) � ��) nr
�) �| �
� ��) ��) � �) � �) �) � (�) pr =�) pr
W�( \| x< �| �� V�) sr i�) sr
��) �|
� � |�) vr
� F} ��) xr
6] Z| ��) �) ��) zr
�=
'p )� � !} ��) |r
�=
'p � )� � +} ��) ~r
t�( ^| �2 U} c�) {| �J } ��) �r
��( Z| �7 �g �| ��) �r
C| �a 'p <_ �) �r
W�( \| �& } #�) } �) �r
W�( \| �& } #�) } 5�) �r
t�( ^| �& } #�) } O�) �r
�=
�l <_ e�) �r
�=
'p � } ��) } ��) �r ��) 6p ��) >p ��) @p
t�( ^| ��) U} ��) �r
��) �| /1 �k ��) �r
�| 7 �| �u �| �2 �} /1 �k �) �r
�| 7 �| �1 }) �� +a �J } �) �r
�| 7 �| � }) �( �4 +a /1 �k +�) �r F�) >p ]�) @p
E �_ �l t�) �r
�| �u �| 1 �1 }) �� ��) ��) �| �J } ��) �r
��( Z| )( �J } �) �r ��) �o
�a 'p <_ � �| P= 7} ��) �r ��) �o ��) p
�� E � �� c�) � �) �r
�a 'p �� � �( � /�) �r
�a 'p �� � f C�) �r
ӽ an �� � �& ]�) � i�) � �) r�) � ��) �r
�g �m � Jm ��) �r ��) �o ��) p ��) �o ��) p �) �o 3�) p S�) �o t�) p ��) �o ��) p ��) �o ��) p �) �o '�) p ?�) p \�) p �) �o ��) p ��) �o ��) p
�=
�l '� �l ��) �r
E_ �k �_ �l �) �r
�_ �l +�) �r D�) �o \�) p
an E_ �l +a �� h q�) �r ��) ֺ
6] �m ��) �p �g �| ��) �r
�=
'p <_ b} .} ��) �r ��) �r ��) @p
�a 'p <_ � (} ��) �r
�) �| 5 �) �r �) �r �) ��
]n E_ �l �) Zn :�) . K�) �r
�) Qq i�) �r ~�) �o
ӽ an ��) �r ��) �q
�� >U . � ��) �r
�� >U ��) �r ��) �r ��) �r ��) � �) � �) �r 0�) �r A�) �o R�) ɲ i�) ɲ
6] �m �7 �g �| }�) . ��) �r
�� ]n ��) �r
�� ]n ��( ��) �r ��) �q
an 7 �| �a
�m �� +a �7 xa$ . �� ��) �r
�| 7 �| �� }) +a ��) ��) �r �) LJ
�| 7 �| � Z � }) �( �4 +a �� 3� s
�� ]n A( �) . �) s
�� ]n 5�) E 9�) s
5�) E
� V� 7 �| G�) s e�) �q
E_ �l <_ )� �" o�) s
E_ �l <_ 6 x< yn �2 d| ��) s
* �| ��
/q ��)
s
� �l ��) ��) s ��) �� ��) �q
�g �m �7 �g �| ��) ��) . ��) s
E_ �l aQ �p
� � �S �m ��) s
ӽ an 7 �| +a 1 ��) �m �� �7 ��) s �) /p �) !�) 7�) O�) b�) s�)
K# � �( � � X�( � �( � � �s) � m�( �
�s) � � '�( �Z E � � � �e) m ��( � ��(
� ��) � K# � �( � � X�( � �( � � )i( � ��(
� '�( �
��) � �
�g( � @ � �
)i( � ��(
� '�( �
��) � K# � �6 � � X�( � �( � � )i( � ��) � �g( m �) � � ��( �: � 9�) � @ S�) ~ H b�) � @
�) ) H {�) � h ��) ) p ��) � � ��( � � ��) � � ��) � � ��) � � ��) � � �) � � �) � � .�) � � B�) � � Z�) � �) �
��) �
��) �k ��) � � ��) � �
�) �- /�) � � 4�) � � 9�) } � [�) � � a�)
� � ��) !s �g( : � ��) s �g( : ��) � �g(
��)
@ �(
� ��)
� X�( �
��) "s �( : ��) #s
�o(
�l
�l �) �$ � 3 @ � �
's (s
)s (s
+s (s
-s (s
/s �l ~o (s &s %s �( 0 � ; �a
�m � �) � �, g ` @ !�) j 1�) H�) \�) v�) ��) ��) ��) ��) ��) �) 6�) J�)
a�) u�) ��)
��) ��) ��) �) 3�) Z�) q�) ��) ��) ��) ��) ��) �) 2�) L�) d�) ��) ��) ��) ��) ! ��) "
�) # $�) $ A�) % Y�) & t�) ' ��) ( ��) ) �) * �) + ��) , �) - *�) . A�) / ^�) 0 ��) 1 ��) 2 �) 3 �) 4 �) 5 �) 6 /�) 7 Q�) 8 l�) 9 ��) : ��) ; ��) < �) = �) > �) ? �) @ 9�) A S�) B r�) C ��) D ��) E ��) F �) G ��) H �) I 3�) J M�) K f�) L ��) M ��) N �) O �) P
�) Q /�) R Y�) S ��) T ��) U ��) V �) W �) X �) Y �) Z 9�) [ S�) \ m�) ] ��) ^ ��) _ �) ` �) a "�) b >�) c W�) d s�) e ��) f ��) g �) h �) �)
�) !�) 8�) Q�) i�) ��) ��) ��) �) �)
��) �) '�)
C�) V�) r�) ��) ��) �) �) ��) �) �� 8s �) �) @ #�) ` /�) � � ;s ;�) 9s M�) f�) ��) @ � � ��( ) ��) � ( ��) � @ X�(
�) � @ �) @ � � ��( �
�) � � * �
* @ L * >s b * ?s �g( � v * � K# � �( � � X�( � �( � � � * @s � * � * � * � * * * A* W* {* 0 ��( )� u @ � Fs @ �* Es �* �* �* �* �* # �n � ) , @ � ) ` � ) h �n p z� %% �( @ �( z� �( @ *�( � �8 ��( @ �* ` * � * � 1 � xL% Is ��( Js oB Ks 8* ` ��( � @ G* � � � Ls � � Kq � J � U* ( � Os # @ ^* � f* 3 �
! Ns k* ~* @ ^* ӽ an @ }) 3 � �* ( J � �* �# �@ Ss @ Qs Ds Rs Ym Ms Hs F| �* 0 � ql �) \s � �C � � �$ 1 @
�| �k [s �* �* �*
* +* O* h* �* �* �* �*
* 2* O* t* �* �* �* �* * B* g* �* �* �* �* * :* c* �* �* �* �* )* V* �* �* �* �* * >* W* v* �* �* �* �* * 5 * U * t * � * � * � *
* "
* F
* `
* }
* �
* �
* �
* * D * q * � * � * � * * �m ' * � @ 0 * ] * � * ZK ' * � @ � * � * � *
� *
* 3
* # X
* @ j
* A |
* B �
* C �
* F �
* � �
* � �
* � �
* � * � &* � 7* � H* � Z* � l*
� ~* � �* � �* � �* � �* � �* �*
* ,* K* @ ��
� @ l* � �* � �) G �*
@ �* � � �* @ �s) �
X�( �
�* � * us 2* �
'�( �
E* � v* ws �* vs �* @ �g( � �* � � �* �
�* �y) � � � � �* � � � � � �* ��( ) * ) �g( � @ �? � � _y) } � !* � � ** @* {s X* @ � � ��( � r* � @ �* |s �* ��( zs G �
)i(
o| � @ '�( � �? � � �* � �* � �k) } �* ) �* � @ �i(
�* � @ 2* �
* �
��( zs "* �
0m(
�� To �( s � 9* �s � � �s � }s xs J* Xi ) }�( ) e*
@ �( � � o* �g( ) �* � �* m~ ( �s) � � �* Xi ) �* � �* m~ ( �s) � � �* �* �s Y� �s * �s �g( �
* ,*
�g( � @ 9* �s L* �
'�( � ^* �
g* �
v* �
e�( ~ �* K# � �( � � X�( � �( � � )i( �Z �i(
�� � @ �( �
��( � �* � � z{( � � �* � � �* � � �� � � �� ys 0m(
�* K# � �( � � X�( � �( � � �s) � m�( �
�s) � � '�( �
�s)
S) � @ �i(
� � @ $�( � ��( }p �*
� ��( �
* �
�l( zp cx) ~s * � K# � �( � � X�( � �( � � )i(
�( � @ '�( �
&* � K# � �( � � X�( � �( � � )i(
�( � @ '�( �
A* � K# � �( � � X�( � �( � � )i(
��( � @ '�( �
[* K# � �( � � X�( � �( � � �*
�( � @ �* �
:�( I �* � K# � �( � � X�( � �( � � )i(
,�( � @ '�( �
�* � K# � �( � � X�( � �( � � )i(
B�( � @ '�( �
�* � K# � �( � � X�( � �( � � )i(
`�) � @ )�) � ��) ~ * K# � �( � � X�( � �( � � )i( �Z �i(
�� � @ �( %m '* � N* � b* � v* � �* �
�* �
)i( � � �* �s �* �s �* @ �* � �* � ή( � ^�( � �* ) �5
@ �* � � ��( � � a�
� X�(
�* � @ )i(
* � @ '�( �Z �s "*
K# � �( � � X�( � �( � � )i( � �s)
S) � @ �i(
� � @ �( %m D* K# � �( � � X�( � �( � � )i( � �s)
S) � @ �i(
� � @ �( � * �
�l( zp _* � �
�g( � @ � �
55 �
'�( �
�* K# � �( � � X�( � �( � � )i( � �s)
S) � @ �i(
� � @ G �
��(
m �* K# � �( � � X�( � �( � � )i( : E � ��( �
�* � � �s) �
�* K# � �( � � X�( � �( � � 2* �
'�( ֪
* � �
�g( � @ � �
2* �
'�( �
:* � K# � �( � � k* � �( � � 2* �
w* �
�* � �
�g( � @ � �
* �
'�( �
�* � K# � �( � � X�( � �( � � * �
'�( �
�* K# � �6 � � X�( � �( � � * �
'�( ֪
* � K# � �( � � X�( � �( � � )i(
��( � @ '�( �
'* @ �g( �
X�( �l H* � � S* � � =] � � b* � � q* � � ~*
� K# � �6 � � X�( � �( � � )i(
�( � @ '�( �
� �s �( � 3 $m �* K# � �( � � X�( � �( � � �*
�( � @ �* �
:�( �
��( �
�( � �* �s �u( ~ �* @ �g( �
X�( ~ �* � � �*
� K# � �6 � � X�( � �( � � )i(
,�( � @ '�( �
� �s �( � 3 .m * K# � �( � � X�( � �( � � �*
�( � @ �* �
:�( I C* � K# � �( � � X�( � �( � � )i(
`* � @ '�( �
e* � K# � �6 � � X�( � �( � � )i(
`�) � @ '�( �
�* K# � �( � � X�( � �( � � �s) � m�( �
�s) � � '�( �
�s)
S) � @ �i(
� � @ G �
��(
m �* � K# � �6 � � X�( � �( � � )i(
��( � @ '�( �
�* � K# � �( � � X�( � �( � � )i( �
'�( � �* � � �* K# � �( � � X�( � �( � � )i( �Z �i(
�� � @ �( %m !* K# � �( � � X�( � �( � � �s) � m�( �
�s) � � '�( �
�s)
S) � @ �i(
� � @ �( � * �
�l( zp =* � �
�g( � @ � �
)i(
�( � @ '�( �
Z* �
�g( � @ � �
)i( � �* �
�i( �s ` �* K# � �( � � X�( � �( � � �*
�( � @ '�( ֪ �* �s �u( ~ �* � �
�g( � @ � �
)i(
,�( � @ '�( �
�* � �
�g( � @ � �
)i(
B�( � @ '�( �
�* �
�g( � @ � �
)i( � :�(
* � @ �i(
* � @ �(
* � @ ��(
(* � @ 3* � K# � �( � � X�( � �( � � O* ) w�( ) 7 � @ '�( �
W* � �
�( � @ � �
��(
� � @ ��( �
{* K# � �6 � � X�( � �( � � �s) � m�( �
�s) � � '�( �
�s)
S) � @ �i( �
�* �s �* � �
�g( � @ � �
)i(
G � @ '�( �
�* � �
�g( � @ � �
)i(
��( � @ '�( �
�* � K# � �( � � X�( � �( � � )i(
�) � @ '�( � ��( � �
* � �
�g( � @ � �
�s) �
'�( �
/ * � K# � �( � � X�( � �( � � )i( �s S *
� n *
� 3 � * � K# � �( � � X�( � �( � � )i( �
'�( � �* � � � * @ � * �
� * � mC) G � � * � � � * � � � * K# � �( � � X�( � �( � � �s) � m�( �
�s) � � '�( � V�) � � �s)
S) � @ �i(
� � @ �* �s � * �g( : \|( � `�( lq ��(
� '� �
* � * �s �s * � � �
X�( �s 0 * � K# � �6 � � X�( � �( � � )i( � �a
�s M * � �
�g( � @ � �
)i(
k * � @ '�( �
s * � K# � �6 � � X�( � �( � � )i(
k * � @ '�( �
� * K# � �( � � X�( � �( � � )i( � * �s � * � �
�g( � @ � �
)i( � �6 � � '�( �
� * � K# � �( � � X�( � �( � � )i( � �6 � � '�( �
� * @ �g( � � � � 55 �
* * < * O * a * y * h �g �| ;� E @ B3 � >� L1 � 9- � >q @ �V @ � * P �a �l � ; @ � * �s � � >q � * 0� os @ � * � � * �| � * �s r�( _l � �s � * � ; 0� qs � � * z
� � * ; � * X A * ; � # * �x ; * ; E * ; � lr ; �A ; � M * X * f * @ X A � ZK � * �s @ �1 }� � t * �� � * �| � * ; � � �D � �A ; � E_ �l � * @ � * A � * B �s � * ( �a �k �a
�m @ �|) � �|) L1 � � * ;� E kv @ >� L1 ` � * �8 � �D @ �A ; � * 8 � � * � �l
�s �l
�s �l
�s �k
�s �k �s �s �s �s �s �l �s �s �s �s
� �s �
�s o �
�s �
�s
E_ �l �' 1s <_ * �s
�a
�m ! * - * > * U� L * � b * �s
E_ �l �� an 7 n � * �s
�|) �s �9 � � * �s
� * �| � �k � * �s � * �� � * �� !* �q !* �s <!* �� R!* ��
E_ �l �F
�s h!* t
�( �m ��) �m �!* t
� D i� �9 E �!* t �!* ��
;� � >� � K# �!*
t
;� � �!* t
�8 �m ��& E �!* t
. ;� � �!* t "* /p
. /1 �k � * �| ;� � "* t
;� E >� E ,"* E �|) � 55 � 0"* t K"* �o \"* �q
;� � p"* t �"* �o
E_ �l }~ �| /1 �k [n �s +a �"* t
E_ �l /1 �k [n �s aQ �s �Q �"* t
2| �' 4s �"* t
�=
'p / 2| <_ 6 �"* "t �"* "t
E_ �k � 8s 6 �9 E � �"* %t
� I ��( Z| y� 't
� I �) �| ?� )t Q� )t
� I W�( \| �� ,t �� ,t
� I E_ �l � 8s # �"* /t Є )t
Qq E_ �l # #* 2t #* ɲ
4s E_ �l <_ *#* 5t
an 7 �| F <| �u 7#* 7t
an �� an �� K#* 9t a#* �o
7 �| F <| 1 �� �| �# x#* <t
2| �=
'p �#* >t
2| �=
'p <_ �#* @t
an 7 n +a �#* Bt
2| � �| �#* Dt
� �| �g \| $* Ft
� �| $* Ht
�g \| 3$* Jt M$* Ht j$* �o
l9 �| �$* Nt �$* p
l9 �| /1 �k �$* Qt
�S �m F� �� �m �$* St
�S �m �� �m �$* Ut �$* �o
l9 �| %* Xt 0%* �o
E_ �l E%* . M%* [t
E_ �l �6 a%* ]t v%* p �%* ɲ �%* bp
� Kq �%* bt �%* ɲ
E_ �l - �l �� � <_ �%* et
R{) �| �� �o �%* gt &* �q
E_ �l <_ $&* jt <&* "t Q&* !p �&* !p �&* !p �&* !p $'* !p S'* !p �'* !p �'* !p �'* !p (* !p ;(* !p h(* �r (* �r
. �(* �� �1 R eM �(* zt
�a 'p � 6 h� . �(* |t
E_ �l �(* Ws �(* ~t �(* ~t )* ~t ))* �o A)* � R)* p
E_ �l �(* Ws � g)* �t
�a
�m �7 3 ��( �> +a �)* �t �)* g�
E_ �l �' 4s / 2| �)* �t
�a �k �' 4s / 2| ��( �)* �t
E_ �l <_ �' 4s / 2| �)* �t
l9 �| ** �} /1 �k ** �t (** p
v �k >** �t W** p
p** E �� 3 -� 3 ӽ an 1 t** �t
E_ �l � Kq �** �t
ӽ an f* 3 �** � 1 �** �t
�� an �** mn �** f* 3 �** � 1 �** �t
ӽ an ^* f* 3 �** � 1 �** . �** �t
ӽ an +* mn �** f* 3 �** � 1 +* �t
E_ �l 7 �| # ^* f* 3 ��( � �** � +* �t
�=
'p ** �o 7+* �t
W�( \| �2 n c�) a& �| � �| �� n ��
n �J } J+* �t
�g \| � �| ^+* �t
�g �m ��( �a �k w+* �t
;� Fn �7 �+* �t
E_ �l �~) \} �g �m ;� � kv � n �+* �t
E_ �l 7 �| �g �m �J } �2 \} ;� � ��
n kv � n �� n �+* �t
ӽ an 1 X� . �+* �t
E_ �l �( n ��( �+* . �+* �t
E_ �l �2 \} �g �m ,* �t
E_ �l 7 �| �g �m P= n ,* �t ,* �t ',* �t Հ �t
E_ �l �g �m ;� � kv 3 7 �| �J } ��
n �~) \} 8,* �t
E_ �l _" n M,* E 7 �| 6] �m R,* �t
E_ �l �J } 3] �m M,* E 7 �| 6] �m j,* �t
E_ �l _" n �( �,* � 7 �| >� � �,* �t
E_ �l �g �m 3] �m �( 7 �| �,* �t
E_ �l �g �m ;� Fn �,* �t
�,* n 7 �| �~) �} �,* �t �,* �t �,* �t -* �t
E_ �l 7 �| �J } �,* n �� n -* �t -* �t
E_ �l �g �m P= n 3-* �t E-* �t
E_ �l �g �m � n �J } � �t
E_ �l �g �m �J } T-* �t
�n C) E ��( < f-* �t
;� Fn x-* �t
E_ �l h �m h �m �-* �t
�-* E ;� Fn �-* �t
�g \| �2 n c�) O* �J } �-* �t
E_ �l �J } �-* �t
G E ;� Fn �-* �t
6] Z| �-* n E_ �l �-* �t �-* �� �-* �o
E_ �k �( � �6 .* �t
E_ �l �g �m ��( 1.* 8.* �t
E_ �k �. �| ��( �6 I.* �t ].* �t
E_ �k �6 q.* �t
E_ �k �( �6 �.* �t
E_ �k ,�( �6 �.* �t
E_ �l �g �m �.* �t
E_ �k
�( �6 �.* �t
E_ �k �( �6 �.* �t �.* �t
�m E_ �l �( /* �t
E_ �l /* � &/* E -/* � 3/* u
E_ �k D/* >� E O/* u
E_ �l �g �m >� Fn j/* u
E_ �k �( . }/* ( �/* u
E_ �k �/* � �6 �/* u
E_ �k �/* �6 �/*
u
E_ �k �( � �6 �/* u
E_ �k �( �6 �/* u
��( | �J } �/* u
W�( \| �2 \} �J } ��( u
�q �| �~) �} �J } 0* u
`| 7 �| �~) �} �J } ��( u
Ah | �J } !0* u 60* .r
�g \| �J } J0* u
�( �| ]0* u
G `| �J } {0* u �0* �q
�g \| �0* "u �0* "u
E_ �l �( n ��( �0* %u �0* � �0* !p
h �m h �m 1* )u
W�( \| �2 _} c�) �� n �J } .1* +u
W�( \| �2 _} c�) �J } T�( -u
G `| A1* �} I1* �J } ��( /u
�g �m � V1* 1u g1* � �1* � �1* �t
W�( \| ��) _} ��) ��) \} �1* 6u
�g �m �( V� E Ia 3 1 � �1* 8u
�a
�m V� E Ia 3 �( �1* �1* �1* f* �1* � 2* :u %2* 8u 92* 8u
�g �m �( V� E Ia 3 1 � M2* >u b2* )u
��( �m � u2* Au �2* p
�2* �n 5 �: s) �2* Du
E_ �l �g �m �R) n �t E � c�) `� �2 n L . �2* Fu
�2 d| �2* Hu �2* p
�2 d| 3* Ku
E_ �l \R .3* Mu <3* �o V3* �o r3* �o �3* p
E �� � �� 3 �; } �3* Su �3* �o
E E_ �l $ �| �� 3 �� 3 1 �3* Vu �3* �q
E_ �l xL% pn ӽ an $ �| 1 �3* Yu
p** E }) 3 4* [u +4* p
W�( \| ��( ^ u| xL% pn :4* . D4* ^u
E_ �l ��( xL% pn :4* . X4* `u
E_ �l �g \| q4* bu
E_ �l ��( �4* un xL% pn :4* . �4* du
ӽ an 7 �| +a �4* fu �4* �o �4* p �4* �r
E_ �l �W sn +a 5* ku
E_ �l �) sn ӽ an X� 5* mu
ӽ an 1 B5* ou g5* ou
ӽ an �� L� X� 1 5* ru
E_ �l �g �m �5* n �5* �5* tu
E_ �k 3] �m � �5* n 7 �| �5* vu �5* /p �5* �o
E_ �l 1 �� Y� . �g �m �5* zu
E_ �l �g �m �2 \}
6* |u "6* zu
E_ �l �g �m �� E �2 \} 66* u
E_ �l �g �m ��) _} K6* �u
>� � x< yn Y6* �u
E_ �l � n G$ �g �m �� n e6* �u q6* �t
E_ �l �g �m �� n � n �2 \} z6* �u �6* �t
�2 \} �6* �u �6* bp
� �| �6* �u
�=
�l 7j k| �t E �6* �u
E_ �l �2 _} c�) �Z �| �6* �u rdma_remove_reason RDMA_REMOVE_DESTROY RDMA_REMOVE_CLOSE RDMA_REMOVE_DRIVER_REMOVE RDMA_REMOVE_ABORT RDMA_REMOVE_DRIVER_FAILURE ucontext_lock default_async_file hw_destroy_rwsem uobjects_lock uobjects umap_lock umaps disassociate_page disassociation_lock mad_hdr ib_mad_hdr base_version mgmt_class class_version class_specific attr_mod MLX5_CMD_OP_QUERY_HCA_CAP MLX5_CMD_OP_QUERY_ADAPTER MLX5_CMD_OP_INIT_HCA MLX5_CMD_OP_TEARDOWN_HCA MLX5_CMD_OP_ENABLE_HCA MLX5_CMD_OP_DISABLE_HCA MLX5_CMD_OP_QUERY_PAGES MLX5_CMD_OP_MANAGE_PAGES MLX5_CMD_OP_SET_HCA_CAP MLX5_CMD_OP_QUERY_ISSI MLX5_CMD_OP_SET_ISSI MLX5_CMD_OP_SET_DRIVER_VERSION MLX5_CMD_OP_QUERY_SF_PARTITION MLX5_CMD_OP_ALLOC_SF MLX5_CMD_OP_DEALLOC_SF MLX5_CMD_OP_SUSPEND_VHCA MLX5_CMD_OP_RESUME_VHCA MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE MLX5_CMD_OP_SAVE_VHCA_STATE MLX5_CMD_OP_LOAD_VHCA_STATE MLX5_CMD_OP_CREATE_MKEY MLX5_CMD_OP_QUERY_MKEY MLX5_CMD_OP_DESTROY_MKEY MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS MLX5_CMD_OP_PAGE_FAULT_RESUME MLX5_CMD_OP_ALLOC_MEMIC MLX5_CMD_OP_DEALLOC_MEMIC MLX5_CMD_OP_MODIFY_MEMIC MLX5_CMD_OP_CREATE_EQ MLX5_CMD_OP_DESTROY_EQ MLX5_CMD_OP_QUERY_EQ MLX5_CMD_OP_GEN_EQE MLX5_CMD_OP_CREATE_CQ MLX5_CMD_OP_DESTROY_CQ MLX5_CMD_OP_QUERY_CQ MLX5_CMD_OP_MODIFY_CQ MLX5_CMD_OP_CREATE_QP MLX5_CMD_OP_DESTROY_QP MLX5_CMD_OP_RST2INIT_QP MLX5_CMD_OP_INIT2RTR_QP MLX5_CMD_OP_RTR2RTS_QP MLX5_CMD_OP_RTS2RTS_QP MLX5_CMD_OP_SQERR2RTS_QP MLX5_CMD_OP_2ERR_QP MLX5_CMD_OP_2RST_QP MLX5_CMD_OP_QUERY_QP MLX5_CMD_OP_SQD_RTS_QP MLX5_CMD_OP_INIT2INIT_QP MLX5_CMD_OP_CREATE_PSV MLX5_CMD_OP_DESTROY_PSV MLX5_CMD_OP_CREATE_SRQ MLX5_CMD_OP_DESTROY_SRQ MLX5_CMD_OP_QUERY_SRQ MLX5_CMD_OP_ARM_RQ MLX5_CMD_OP_CREATE_XRC_SRQ MLX5_CMD_OP_DESTROY_XRC_SRQ MLX5_CMD_OP_QUERY_XRC_SRQ MLX5_CMD_OP_ARM_XRC_SRQ MLX5_CMD_OP_CREATE_DCT MLX5_CMD_OP_DESTROY_DCT MLX5_CMD_OP_DRAIN_DCT MLX5_CMD_OP_QUERY_DCT MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION MLX5_CMD_OP_CREATE_XRQ MLX5_CMD_OP_DESTROY_XRQ MLX5_CMD_OP_QUERY_XRQ MLX5_CMD_OP_ARM_XRQ MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS MLX5_CMD_OP_RELEASE_XRQ_ERROR MLX5_CMD_OP_MODIFY_XRQ MLX5_CMD_OP_QUERY_ESW_FUNCTIONS MLX5_CMD_OP_QUERY_VPORT_STATE MLX5_CMD_OP_MODIFY_VPORT_STATE MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT MLX5_CMD_OP_QUERY_ROCE_ADDRESS MLX5_CMD_OP_SET_ROCE_ADDRESS MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT MLX5_CMD_OP_QUERY_HCA_VPORT_GID MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY MLX5_CMD_OP_QUERY_VNIC_ENV MLX5_CMD_OP_QUERY_VPORT_COUNTER MLX5_CMD_OP_ALLOC_Q_COUNTER MLX5_CMD_OP_DEALLOC_Q_COUNTER MLX5_CMD_OP_QUERY_Q_COUNTER MLX5_CMD_OP_SET_MONITOR_COUNTER MLX5_CMD_OP_ARM_MONITOR_COUNTER MLX5_CMD_OP_SET_PP_RATE_LIMIT MLX5_CMD_OP_QUERY_RATE_LIMIT MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT MLX5_CMD_OP_CREATE_QOS_PARA_VPORT MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT MLX5_CMD_OP_ALLOC_PD MLX5_CMD_OP_DEALLOC_PD MLX5_CMD_OP_ALLOC_UAR MLX5_CMD_OP_DEALLOC_UAR MLX5_CMD_OP_CONFIG_INT_MODERATION MLX5_CMD_OP_ACCESS_REG MLX5_CMD_OP_ATTACH_TO_MCG MLX5_CMD_OP_DETACH_FROM_MCG MLX5_CMD_OP_GET_DROPPED_PACKET_LOG MLX5_CMD_OP_MAD_IFC MLX5_CMD_OP_QUERY_MAD_DEMUX MLX5_CMD_OP_SET_MAD_DEMUX MLX5_CMD_OP_NOP MLX5_CMD_OP_ALLOC_XRCD MLX5_CMD_OP_DEALLOC_XRCD MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN MLX5_CMD_OP_QUERY_CONG_STATUS MLX5_CMD_OP_MODIFY_CONG_STATUS MLX5_CMD_OP_QUERY_CONG_PARAMS MLX5_CMD_OP_MODIFY_CONG_PARAMS MLX5_CMD_OP_QUERY_CONG_STATISTICS MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT MLX5_CMD_OP_SET_L2_TABLE_ENTRY MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY MLX5_CMD_OP_SET_WOL_ROL MLX5_CMD_OP_QUERY_WOL_ROL MLX5_CMD_OP_CREATE_LAG MLX5_CMD_OP_MODIFY_LAG MLX5_CMD_OP_QUERY_LAG MLX5_CMD_OP_DESTROY_LAG MLX5_CMD_OP_CREATE_VPORT_LAG MLX5_CMD_OP_DESTROY_VPORT_LAG MLX5_CMD_OP_CREATE_TIR MLX5_CMD_OP_MODIFY_TIR MLX5_CMD_OP_DESTROY_TIR MLX5_CMD_OP_QUERY_TIR MLX5_CMD_OP_CREATE_SQ MLX5_CMD_OP_MODIFY_SQ MLX5_CMD_OP_DESTROY_SQ MLX5_CMD_OP_QUERY_SQ MLX5_CMD_OP_CREATE_RQ MLX5_CMD_OP_MODIFY_RQ MLX5_CMD_OP_SET_DELAY_DROP_PARAMS MLX5_CMD_OP_DESTROY_RQ MLX5_CMD_OP_QUERY_RQ MLX5_CMD_OP_CREATE_RMP MLX5_CMD_OP_MODIFY_RMP MLX5_CMD_OP_DESTROY_RMP MLX5_CMD_OP_QUERY_RMP MLX5_CMD_OP_CREATE_TIS MLX5_CMD_OP_MODIFY_TIS MLX5_CMD_OP_DESTROY_TIS MLX5_CMD_OP_QUERY_TIS MLX5_CMD_OP_CREATE_RQT MLX5_CMD_OP_MODIFY_RQT MLX5_CMD_OP_DESTROY_RQT MLX5_CMD_OP_QUERY_RQT MLX5_CMD_OP_SET_FLOW_TABLE_ROOT MLX5_CMD_OP_CREATE_FLOW_TABLE MLX5_CMD_OP_DESTROY_FLOW_TABLE MLX5_CMD_OP_QUERY_FLOW_TABLE MLX5_CMD_OP_CREATE_FLOW_GROUP MLX5_CMD_OP_DESTROY_FLOW_GROUP MLX5_CMD_OP_QUERY_FLOW_GROUP MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY MLX5_CMD_OP_ALLOC_FLOW_COUNTER MLX5_CMD_OP_DEALLOC_FLOW_COUNTER MLX5_CMD_OP_QUERY_FLOW_COUNTER MLX5_CMD_OP_MODIFY_FLOW_TABLE MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT MLX5_CMD_OP_FPGA_CREATE_QP MLX5_CMD_OP_FPGA_MODIFY_QP MLX5_CMD_OP_FPGA_QUERY_QP MLX5_CMD_OP_FPGA_DESTROY_QP MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS MLX5_CMD_OP_CREATE_GENERAL_OBJECT MLX5_CMD_OP_MODIFY_GENERAL_OBJECT MLX5_CMD_OP_QUERY_GENERAL_OBJECT MLX5_CMD_OP_DESTROY_GENERAL_OBJECT MLX5_CMD_OP_CREATE_UCTX MLX5_CMD_OP_DESTROY_UCTX MLX5_CMD_OP_CREATE_UMEM MLX5_CMD_OP_DESTROY_UMEM MLX5_CMD_OP_SYNC_STEERING MLX5_CMD_OP_QUERY_VHCA_STATE MLX5_CMD_OP_MODIFY_VHCA_STATE MLX5_CMD_OP_SYNC_CRYPTO MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS MLX5_CMD_OP_GENERATE_WQE MLX5_CMD_OPCODE_QUERY_VUID MLX5_CMD_OP_MAX mlx5_ifc_cmd_hca_cap_bits reserved_at_0 page_request_disable abs_native_port_num reserved_at_8 shared_object_to_user_object_allowed reserved_at_13 vhca_resource_manager hca_cap_2 create_lag_when_not_master_up event_on_vhca_state_teardown_request event_on_vhca_state_in_use event_on_vhca_state_active event_on_vhca_state_allocated event_on_vhca_state_invalid reserved_at_28 vhca_id reserved_at_40 log_max_srq_sz log_max_qp_sz event_cap reserved_at_91 isolate_vl_tc_new reserved_at_94 prio_tag_required reserved_at_99 log_max_qp reserved_at_a0 ece_support reserved_at_a4 reg_c_preserve reserved_at_aa log_max_srq reserved_at_b0 uplink_follow ts_cqe_to_dest_cqn reserved_at_b3 go_back_n reserved_at_ba max_sgl_for_optimized_performance log_max_cq_sz relaxed_ordering_write_umr relaxed_ordering_read_umr reserved_at_d2 virtio_net_device_emualtion_manager virtio_blk_device_emualtion_manager log_max_cq log_max_eq_sz relaxed_ordering_write relaxed_ordering_read_pci_enabled log_max_mkey reserved_at_f0 terminate_scatter_list_mkey repeated_mkey dump_fill_mkey reserved_at_f9 fast_teardown log_max_eq max_indirection fixed_buffer_size log_max_mrw_sz force_teardown reserved_at_111 log_max_bsf_list_size umr_extended_translation_offset null_mkey log_max_klm_list_size reserved_at_120 qpc_extension reserved_at_123 log_max_ra_req_dc reserved_at_130 eth_wqe_too_small reserved_at_133 vnic_env_cq_overrun log_max_ra_res_dc reserved_at_140 release_all_pages must_not_use reserved_at_147 roce_accl log_max_ra_req_qp reserved_at_150 log_max_ra_res_qp end_pad cc_query_allowed cc_modify_allowed cache_line_128byte reserved_at_165 rts2rts_qp_counters_set_id reserved_at_16a vnic_env_int_rq_oob sbcam_reg reserved_at_16e qcam_reg gid_table_size out_of_seq_cnt vport_counters retransmission_q_counters modify_rq_counter_set_id rq_delay_drop max_qp_cnt pkey_table_size vport_group_manager vhca_group_manager ib_virt eth_virt vnic_env_queue_counters ets nic_flow_table eswitch_manager device_memory mcam_reg pcam_reg port_module_event enhanced_error_q_counters ports_check reserved_at_1b3 disable_link_up beacon_led reserved_at_1c0 pps_modify log_max_msg reserved_at_1c8 max_tc temp_warn_event general_notification_event reserved_at_1d3 fpga rol_s rol_g reserved_at_1d8 wol_s wol_g wol_a wol_b wol_m wol_u wol_p stat_rate_support reserved_at_1f0 pci_sync_for_fw_update_event reserved_at_1f2 init2_lag_tx_port_affinity reserved_at_1fa wqe_based_flow_table_update_cap cqe_version compact_address_vector striding_rq reserved_at_202 ipoib_enhanced_offloads ipoib_basic_offloads reserved_at_205 repeated_block_disabled umr_modify_entity_size_disabled umr_modify_atomic_disabled umr_indirect_mkey_disabled umr_fence dc_req_scat_data_cqe reserved_at_20d drain_sigerr cmdif_checksum sigerr_cqe reserved_at_213 wq_signature sctr_data_cqe reserved_at_216 sho tph dct eth_net_offloads reserved_at_21f cq_oi cq_resize cq_moderation cq_period_mode_modify reserved_at_224 cq_eq_remap block_lb_mc reserved_at_229 scqe_break_moderation cq_period_start_from_cqe reserved_at_22d apm vector_calc umr_ptr_rlky imaicl qp_packet_based reserved_at_233 qkv pkv set_deth_sqpn reserved_at_239 ud uar_4k reserved_at_241 fl_rc_qp_when_roce_disabled regexp_params uar_sz port_selection_cap nic_cap_reg umem_uid_0 reserved_at_253 log_pg_sz bf pad_tx_eth_packet reserved_at_263 mkey_by_name reserved_at_267 log_bf_reg_size reserved_at_270 qp_error_syndrome reserved_at_274 lag_dct lag_tx_port_affinity lag_native_fdb_selection reserved_at_27a lag_master num_lag_ports reserved_at_280 max_wqe_sz_sq reserved_at_2a0 shampo reserved_at_2ac max_wqe_sz_rq max_flow_counter_31_16 max_wqe_sz_sq_dc reserved_at_2e0 max_qp_mcg reserved_at_300 flow_counter_bulk_alloc log_max_mcg reserved_at_320 log_max_transport_domain reserved_at_328 relaxed_ordering_read log_max_pd dp_ordering_ooo_all_ud dp_ordering_ooo_all_uc dp_ordering_ooo_all_xrc dp_ordering_ooo_all_dc dp_ordering_ooo_all_rc pcie_reset_using_hotreset_method pci_sync_for_fw_update_with_driver_unload vnic_env_cnt_steering_fail vport_counter_local_loopback q_counter_aggregation q_counter_other_vport log_max_xrcd nic_receive_steering_discard receive_discard_vport_down transmit_discard_vport_down eq_overrun_count reserved_at_344 invalid_command_count quota_exceeded_count reserved_at_347 log_max_flow_counter_bulk max_flow_counter_15_0 reserved_at_360 log_max_rq reserved_at_368 log_max_sq reserved_at_370 log_max_tir reserved_at_378 log_max_tis basic_cyclic_rcv_wqe reserved_at_381 log_max_rmp reserved_at_388 log_max_rqt reserved_at_390 log_max_rqt_size reserved_at_398 log_max_tis_per_sq ext_stride_num_range roce_rw_supported log_max_current_uc_list_wr_supported log_max_stride_sz_rq reserved_at_3a8 log_min_stride_sz_rq reserved_at_3b0 log_max_stride_sz_sq reserved_at_3b8 log_min_stride_sz_sq hairpin reserved_at_3c1 log_max_hairpin_queues reserved_at_3c8 log_max_hairpin_wq_data_sz reserved_at_3d0 log_max_hairpin_num_packets reserved_at_3d8 log_max_wq_sz nic_vport_change_event disable_local_lb_uc disable_local_lb_mc log_min_hairpin_wq_data_sz reserved_at_3e8 silent_mode vhca_state log_max_vlan_list reserved_at_3f0 log_max_current_mc_list reserved_at_3f8 log_max_current_uc_list general_obj_types sq_ts_format rq_ts_format steering_format_version create_qp_start_hint reserved_at_460 ats cross_vhca_rqt log_max_uctx reserved_at_468 ipsec_offload log_max_umem reserved_at_480 tls_tx tls_rx log_max_l2_table reserved_at_488 log_uar_page_sz reserved_at_4a0 device_frequency_mhz device_frequency_khz reserved_at_500 num_of_uars_per_page flex_parser_protocols max_geneve_tlv_options reserved_at_568 max_geneve_tlv_option_data_len reserved_at_570 adv_virtualization reserved_at_57a reserved_at_580 log_max_dci_stream_channels reserved_at_590 log_max_dci_errored_streams reserved_at_598 reserved_at_5a0 enhanced_cqe_compression reserved_at_5b1 crossing_vhca_mkey log_max_dek reserved_at_5b8 mini_cqe_resp_stride_index cqe_128_always cqe_compression_128 cqe_compression cqe_compression_timeout cqe_compression_max_num reserved_at_5e0 flex_parser_id_gtpu_dw_0 reserved_at_5ec rndv_offload_rc rndv_offload_dc log_tag_matching_list_sz reserved_at_5f8 log_max_xrq affiliate_nic_vport_criteria native_port_num num_vhca_ports flex_parser_id_gtpu_teid reserved_at_61c sw_owner_id reserved_at_61f max_num_of_monitor_counters num_ppcnt_monitor_counters max_num_sf num_q_monitor_counters reserved_at_660 sf_set_partition reserved_at_682 log_max_sf apu reserved_at_689 migration reserved_at_68e log_min_sf_size max_num_sf_partitions uctx_cap reserved_at_6c0 flex_parser_id_geneve_tlv_option_0 flex_parser_id_icmp_dw1 flex_parser_id_icmp_dw0 flex_parser_id_icmpv6_dw1 flex_parser_id_icmpv6_dw0 flex_parser_id_outer_first_mpls_over_gre flex_parser_id_outer_first_mpls_over_udp_label max_num_match_definer sf_base_id flex_parser_id_gtpu_dw_2 flex_parser_id_gtpu_first_ext_dw_0 num_total_dynamic_vf_msix reserved_at_720 dynamic_msix_table_size reserved_at_740 min_dynamic_vf_msix_table_size reserved_at_750 data_direct reserved_at_753 max_dynamic_vf_msix_table_size reserved_at_760 log_max_num_header_modify_argument log_header_modify_argument_granularity_offset log_header_modify_argument_granularity reserved_at_770 log_header_modify_argument_max_alloc reserved_at_778 vhca_tunnel_commands match_definer_format_supported mlx5_ifc_query_vuid_in_bits reserved_at_20 query_vfs_vuid reserved_at_62 mlx5_ifc_query_special_contexts_out_bits resd_lkey mlx5_ifc_query_special_contexts_in_bits reserved_at_10 op_mod mlx5_ifc_query_cong_params_in_bits cong_protocol reserved_at_60 mlx5_ifc_mad_ifc_out_bits response_mad_packet mlx5_ifc_mad_ifc_in_bits remote_lid plane_index mad mlx5_ifc_detach_from_mcg_in_bits qpn multicast_gid mlx5_ifc_destroy_tis_in_bits tisn mlx5_ifc_destroy_tir_in_bits tirn mlx5_ifc_destroy_rqt_in_bits rqtn mlx5_ifc_dealloc_xrcd_in_bits mlx5_ifc_dealloc_uar_in_bits uar mlx5_ifc_dealloc_transport_domain_in_bits transport_domain mlx5_ifc_dealloc_pd_in_bits mlx5_ifc_attach_to_mcg_in_bits mlx5_ifc_alloc_xrcd_out_bits mlx5_ifc_alloc_xrcd_in_bits mlx5_ifc_alloc_uar_out_bits mlx5_ifc_alloc_uar_in_bits mlx5_ifc_alloc_transport_domain_out_bits mlx5_ifc_alloc_transport_domain_in_bits mlx5_cmd_layout in_ptr out_ptr status_own health_buffer assert_var assert_exit_ptr assert_callra rfr_severity irisc_index ext_synd mlx5_init_seg fw_rev cmdif_rev_fw_sub cmdq_addr_h cmdq_addr_l_sz cmd_dbell initializing cmd_exec_to cmd_q_init_to internal_timer_h internal_timer_l health_counter real_time_h real_time_l rsvd5 ieee1588_clk ieee1588_clk_type clr_intx mlx5_cap_type MLX5_CAP_GENERAL MLX5_CAP_ETHERNET_OFFLOADS MLX5_CAP_ODP MLX5_CAP_ATOMIC MLX5_CAP_ROCE MLX5_CAP_IPOIB_OFFLOADS MLX5_CAP_IPOIB_ENHANCED_OFFLOADS MLX5_CAP_FLOW_TABLE MLX5_CAP_ESWITCH_FLOW_TABLE MLX5_CAP_ESWITCH MLX5_CAP_QOS MLX5_CAP_DEBUG MLX5_CAP_RESERVED_14 MLX5_CAP_DEV_MEM MLX5_CAP_RESERVED_16 MLX5_CAP_TLS MLX5_CAP_VDPA_EMULATION MLX5_CAP_DEV_EVENT MLX5_CAP_IPSEC MLX5_CAP_CRYPTO MLX5_CAP_SHAMPO MLX5_CAP_MACSEC MLX5_CAP_GENERAL_2 MLX5_CAP_PORT_SELECTION MLX5_CAP_ADV_VIRTUALIZATION MLX5_CAP_NUM mlx5_nb port_state_policy MLX5_POLICY_DOWN MLX5_POLICY_UP MLX5_POLICY_FOLLOW MLX5_POLICY_INVALID mlx5_coredev_type MLX5_COREDEV_PF MLX5_COREDEV_VF MLX5_COREDEV_SF mlx5_core_dev coredev_type pci_status_mutex pci_status rev_id board_id iseg_base iseg bar_addr intf_state_mutex intf_state issi mlx5e_res geneve clock_info rsc_dump vsc_addr hv_vhca num_block_tc num_block_ipsec macsec_fs macsec_nh num_ipsec_offloads wc_state wc_state_lock mlx5_cmdif_state MLX5_CMDIF_STATE_UNINITIALIZED MLX5_CMDIF_STATE_UP MLX5_CMDIF_STATE_DOWN mlx5_cmd_first mlx5_cmd_msg cmd_msg_cache max_inbox_size num_ent mlx5_cmd_mailbox mlx5_cmd_debug cmdif_rev log_sz log_stride max_reg_cmds pages_sem throttle_sem mlx5_cmd cmd_alloc_buf alloc_dma token_lock wq_name allowed_opcode ent_arr dbg checksum_disabled mlx5_cmd_work_ent uout uout_size cb_timeout_work slotted lay page_queue ts1 ts2 mlx5_uars_page bfregs reg_bitmap fp_bitmap reg_avail fp_avail mlx5_bfreg_head mlx5_bfreg_data reg_head wc_head mlx5_sq_bfreg mlx5_core_health miss_counter fatal_error crdump_size fatal_report_work report_work fw_reporter fw_fatal_reporter vnic_reporter update_fw_log_ts_work mlx5_vf_context port_guid port_guid_valid node_guid_valid mlx5_core_sriov vfs_ctx max_ec_vfs mlx5_rl_entry rl_raw dedicated mlx5_rl_table rl_lock rl_entry mlx5_core_roce allow_rule mlx5_flow_table mlx5_flow_group mlx5_flow_handle mlx5_adev mlx5_debugfs_entries qp_debugfs eq_debugfs cq_debugfs cmdif_debugfs pages_debugfs lag_debugfs mlx5_priv irq_table eq_table pg_nb pg_wq page_root_xa reg_pages fw_pages page_counters fw_pages_alloc_failed give_pages_dropped reclaim_pages_discard alloc_mutex pgdir_mutex pgdir_list adev_idx sw_vhca_id vhca_events steering mpfs eswitch devc hca_devcom_comp fw_reset fc_stats rl_table ft_pool vhca_state_notifier sf_dev_table parent_mdev sf_hw_table sf_table lag_nh mlx5_irq_table mlx5_eq_table mlx5_events mlx5_vhca_events mlx5_flow_steering mlx5_mpfs mlx5_eswitch mlx5_lag mlx5_devcom_dev mlx5_devcom_comp_dev mlx5_fw_reset mlx5_fc_stats mlx5_ft_pool mlx5_vhca_state_notifier mlx5_sf_dev_table mlx5_sf_hw_table mlx5_sf_table mlx5_device_state MLX5_DEVICE_STATE_UP MLX5_DEVICE_STATE_INTERNAL_ERROR mlx5_pci_status MLX5_PCI_STATUS_DISABLED MLX5_PCI_STATUS_ENABLED mlx5_td tirs_list tdn mlx5e_hw_objs mkey bfreg tisn_valid mlx5e_resources hw_objs uplink_netdev uplink_netdev_lock dek_priv mlx5_crypto_dek_priv mlx5_rsvd_gids mlx5_pps pin_caps out_work min_npps_period min_out_pulse_duration_ns mlx5_timer nominal_c_mult overflow_period mlx5_clock pps_nb ptp_info pps_info mlx5_profile num_cmd_caches mr_cache mlx5_hca_cap mlx5_wc_state MLX5_WC_STATE_UNINITIALIZED MLX5_WC_STATE_UNSUPPORTED MLX5_WC_STATE_SUPPORTED hca pcam mcam qcam embedded_cpu reserved_gids roce_en mlx5_timeouts mlx5_dm memic_alloc_pages mlx5_vxlan mlx5_geneve mlx5_fpga_device mlx5_ib_clock_info mlx5_fw_tracer mlx5_rsc_dump mlx5_hv_vhca mlx5_hwmon mlx5_macsec_fs mlx5_sd mlx5_cmd_cbk_t mlx5_async_ctx num_inflight inflight_done mlx5_fc rdma_lookup_mode UVERBS_LOOKUP_READ UVERBS_LOOKUP_WRITE UVERBS_LOOKUP_DESTROY uverbs_obj_type_class alloc_begin alloc_commit alloc_abort lookup_get lookup_put destroy_hw remove_handle swap_uobjects uverbs_obj_type type_class ib_uverbs_device ib_uverbs_async_event_file num_elems enum_def uverbs_attr_spec zero_trailing alloc_and_copy mandatory is_udata objs_arr uverbs_attr_def uverbs_method_def uverbs_object_def type_attrs num_methods object_id command_num is_ex has_udata has_resp object_start func_is_supported func_write chain_obj_tree needs_fn_offset uverbs_ptr_attr uattr_idx enum_id uverbs_obj_attr attr_elm uverbs_api_attr uverbs_objs_arr_attr ptr_attr obj_attr objs_arr_attr uverbs_attr driver_udata ucore attr_present uverbs_attr_bundle_hdr mlx5_srq_table mlx5_qp_table dct_xa mlx5_ib_anchor fg_goto_table fg_drop rule_goto_table rule_drop rule_goto_table_ref mlx5_ib_flow_prio mlx5_ib_dev data_direct_dev data_direct_lock mdev_events lag_events cap_mask_mutex ib_active lag_active fill_delay umrc devr mkey_var slow_path_mutex odp_max_size odp_eq_mutex odp_pf_eq odp_mkeys flow_db reset_flow_resource_lock data_direct_mr_list fp_bfreg delay_drop ib_dev_list devx_whitelist_uid srq_table qp_table async_ctx devx_event_table var_table pkey_table_len lag_ports mkeys ddr macsec num_plane smi_dev sub_dev_name mlx5_ib_flow_db prios egress_prios sniffer egress rdma_rx rdma_tx opfcs lag_demux_ft mlx5_ib_gsi_qp rx_qp outstanding_wrs outstanding_pi outstanding_ci num_qps tx_qps mlx5_ib_gsi_wr umr_common mlx5_mkey_cache rb_lock fs_root last_add mlx5_ib_port_resources pkey_change_work mlx5_data_direct_resources mlx5_ib_resources c0 xrcdn0 xrcdn1 p0 s0 srq_lock mlx5_ib_op_fc mlx5_ib_counters num_q_counters num_cong_counters num_ext_ppcnt_counters num_op_counters set_id mlx5_ib_multiport mpi_lock mlx5_ib_multiport_info unref_comp mdev_refcnt unaffiliate mlx5_roce mdev_nb tracking_netdev tx_port_affinity mlx5_ib_port dbg_cc_params mlx5_ib_dbg_cc_params mlx5_eswitch_rep mlx5_reserved_gids mlx5_ib_dbg_param mlx5_ib_delay_drop delay_drop_work events_cnt rqs_cnt dir_debugfs mlx5_ib_stage mlx5_ib_profile mlx5_ib_lb_state user_td qps mlx5_ib_pf_eq irq_nb mlx5_eq mlx5_devx_event_table devx_nb event_xa_lock event_xa mlx5_var_table bitmap_lock hw_start_addr stride_size num_var_hw_entries mlx5_port_caps has_smi ext_port_cap mlx5_special_mkeys mlx5_macsec macsec_devices_list blocking_events_nb mlx5_data_direct_dev ib_uverbs_ex_create_cq_flags IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN IB_USER_MAD_USER_RMPP ib_ah_flags IB_AH_GRH ib_rate IB_RATE_PORT_CURRENT IB_RATE_2_5_GBPS IB_RATE_5_GBPS IB_RATE_10_GBPS IB_RATE_20_GBPS IB_RATE_30_GBPS IB_RATE_40_GBPS IB_RATE_60_GBPS IB_RATE_80_GBPS IB_RATE_120_GBPS IB_RATE_14_GBPS IB_RATE_56_GBPS IB_RATE_112_GBPS IB_RATE_168_GBPS IB_RATE_25_GBPS IB_RATE_100_GBPS IB_RATE_200_GBPS IB_RATE_300_GBPS IB_RATE_28_GBPS IB_RATE_50_GBPS IB_RATE_400_GBPS IB_RATE_600_GBPS IB_RATE_800_GBPS ib_qp_create_flags IB_QP_CREATE_IPOIB_UD_LSO IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK IB_QP_CREATE_CROSS_CHANNEL IB_QP_CREATE_MANAGED_SEND IB_QP_CREATE_MANAGED_RECV IB_QP_CREATE_NETIF_QP IB_QP_CREATE_INTEGRITY_EN IB_QP_CREATE_NETDEV_USE IB_QP_CREATE_SCATTER_FCS IB_QP_CREATE_CVLAN_STRIPPING IB_QP_CREATE_SOURCE_QPN IB_QP_CREATE_PCI_WRITE_END_PADDING IB_QP_CREATE_RESERVED_START IB_QP_CREATE_RESERVED_END ib_qp_attr_mask IB_QP_STATE IB_QP_CUR_STATE IB_QP_EN_SQD_ASYNC_NOTIFY IB_QP_ACCESS_FLAGS IB_QP_PKEY_INDEX IB_QP_PORT IB_QP_QKEY IB_QP_AV IB_QP_PATH_MTU IB_QP_TIMEOUT IB_QP_RETRY_CNT IB_QP_RNR_RETRY IB_QP_RQ_PSN IB_QP_MAX_QP_RD_ATOMIC IB_QP_ALT_PATH IB_QP_MIN_RNR_TIMER IB_QP_SQ_PSN IB_QP_MAX_DEST_RD_ATOMIC IB_QP_PATH_MIG_STATE IB_QP_CAP IB_QP_DEST_QPN IB_QP_RESERVED1 IB_QP_RESERVED2 IB_QP_RESERVED3 IB_QP_RESERVED4 IB_QP_RATE_LIMIT IB_QP_ATTR_STANDARD_BITS ib_rdma_wr remote_addr ib_access_flags IB_ACCESS_LOCAL_WRITE IB_ACCESS_REMOTE_WRITE IB_ACCESS_REMOTE_READ IB_ACCESS_REMOTE_ATOMIC IB_ACCESS_MW_BIND IB_ZERO_BASED IB_ACCESS_ON_DEMAND IB_ACCESS_HUGETLB IB_ACCESS_RELAXED_ORDERING IB_ACCESS_FLUSH_GLOBAL IB_ACCESS_FLUSH_PERSISTENT IB_ACCESS_OPTIONAL IB_ACCESS_SUPPORTED ib_raw_packet_caps IB_RAW_PACKET_CAP_CVLAN_STRIPPING IB_RAW_PACKET_CAP_SCATTER_FCS IB_RAW_PACKET_CAP_IP_CSUM IB_RAW_PACKET_CAP_DELAY_DROP ib_wq_flags IB_WQ_FLAGS_CVLAN_STRIPPING IB_WQ_FLAGS_SCATTER_FCS IB_WQ_FLAGS_DELAY_DROP IB_WQ_FLAGS_PCI_WRITE_END_PADDING ib_wq_attr_mask IB_WQ_STATE IB_WQ_CUR_STATE IB_WQ_FLAGS ib_umem owning_mm is_odp is_dmabuf mlx5_ifc_flow_table_fields_supported_bits outer_dmac outer_smac outer_ether_type outer_ip_version outer_first_prio outer_first_cfi outer_first_vid outer_ipv4_ttl outer_second_prio outer_second_cfi outer_second_vid reserved_at_b outer_sip outer_dip outer_frag outer_ip_protocol outer_ip_ecn outer_ip_dscp outer_udp_sport outer_udp_dport outer_tcp_sport outer_tcp_dport outer_tcp_flags outer_gre_protocol outer_gre_key outer_vxlan_vni outer_geneve_vni outer_geneve_oam outer_geneve_protocol_type outer_geneve_opt_len source_vhca_port source_eswitch_port inner_dmac inner_smac inner_ether_type inner_ip_version inner_first_prio inner_first_cfi inner_first_vid reserved_at_27 inner_second_prio inner_second_cfi inner_second_vid reserved_at_2b inner_sip inner_dip inner_frag inner_ip_protocol inner_ip_ecn inner_ip_dscp inner_udp_sport inner_udp_dport inner_tcp_sport inner_tcp_dport inner_tcp_flags reserved_at_37 geneve_tlv_option_0_data geneve_tlv_option_0_exist reserved_at_42 outer_first_mpls_over_udp outer_first_mpls_over_gre inner_first_mpls outer_first_mpls reserved_at_55 outer_esp_spi reserved_at_58 bth_dst_qp reserved_at_5b metadata_reg_c_7 metadata_reg_c_6 metadata_reg_c_5 metadata_reg_c_4 metadata_reg_c_3 metadata_reg_c_2 metadata_reg_c_1 metadata_reg_c_0 mlx5_ifc_flow_table_fields_supported_2_bits inner_l4_type outer_l4_type reserved_at_4 bth_opcode reserved_at_f tunnel_header_0_1 reserved_at_11 mlx5_ifc_flow_table_prop_layout_bits ft_support reserved_at_1 flow_counter flow_modify_en modify_root identified_miss_table_mode flow_table_modify reformat decap reset_root_to_default pop_vlan push_vlan reserved_at_c pop_vlan_2 push_vlan_2 reformat_and_vlan_action sw_owner reformat_l3_tunnel_to_l2 reformat_l2_to_l3_tunnel reformat_and_modify_action ignore_flow_level reserved_at_16 table_miss_action_domain termination_table reformat_and_fwd_to_table reserved_at_1a ipsec_encrypt ipsec_decrypt sw_owner_v2 reserved_at_1f termination_table_raw_traffic reserved_at_21 log_max_ft_size log_max_modify_header_context max_modify_header_actions max_ft_level reformat_add_esp_trasport reformat_l2_to_l3_esp_tunnel reformat_add_esp_transport_over_udp reformat_del_esp_trasport reformat_l3_esp_tunnel_to_l2 reformat_del_esp_transport_over_udp execute_aso reserved_at_47 reformat_insert reformat_remove macsec_encrypt macsec_decrypt reserved_at_66 reformat_add_macsec reformat_remove_macsec reparse reserved_at_6b cross_vhca_object reformat_l2_to_l3_audp_tunnel reformat_l3_audp_tunnel_to_l2 ignore_flow_level_rtc_valid reserved_at_70 log_max_ft_num reserved_at_80 log_max_flow_counter log_max_destination log_max_flow reserved_at_c0 ft_field_support ft_field_bitmask_support mlx5_ifc_cmd_pas_bits pa_h pa_l reserved_at_34 mlx5_ifc_ads_bits free_ar reserved_at_2 mlid rlid ack_timeout reserved_at_45 src_addr_index reserved_at_50 stat_rate rgid_rip reserved_at_100 f_dscp f_ecn reserved_at_106 f_eth_prio udp_sport dei_cfi eth_prio vhca_port_num rmac_47_32 rmac_31_0 mlx5_ifc_flow_table_nic_cap_bits nic_rx_multi_path_tirs nic_rx_multi_path_tirs_fts allow_sniffer_and_nic_rx_shared_tir reserved_at_3 sw_owner_reformat_supported encap_general_header log_max_packet_reformat_context reserved_at_30 max_encap_header_size flow_table_properties_nic_receive flow_table_properties_nic_receive_rdma flow_table_properties_nic_receive_sniffer flow_table_properties_nic_transmit flow_table_properties_nic_transmit_rdma flow_table_properties_nic_transmit_sniffer reserved_at_e00 ft_field_support_2_nic_receive reserved_at_1480 ft_field_support_2_nic_receive_rdma reserved_at_1580 ft_field_support_2_nic_transmit_rdma reserved_at_1880 sw_steering_nic_rx_action_drop_icm_address sw_steering_nic_tx_action_drop_icm_address sw_steering_nic_tx_action_allow_icm_address reserved_at_20c0 mlx5_ifc_port_selection_cap_bits port_select_flow_table port_select_flow_table_bypass flow_table_properties_port_selection ft_field_support_2_port_selection mlx5_ifc_qos_cap_bits packet_pacing esw_scheduling esw_bw_share esw_rate_limit packet_pacing_burst_bound packet_pacing_typical_size reserved_at_7 nic_sq_scheduling nic_bw_share nic_rate_limit packet_pacing_uid log_esw_max_sched_depth esw_cross_esw_sched reserved_at_2a log_max_qos_nic_queue_group packet_pacing_max_rate packet_pacing_min_rate log_esw_max_rate_limit packet_pacing_rate_table_size esw_element_type esw_tsar_type max_qos_para_vport max_tsar_bw_share nic_element_type nic_tsar_type log_meter_aso_granularity reserved_at_128 log_meter_aso_max_alloc log_max_num_meter_aso reserved_at_138 mlx5_ifc_per_protocol_networking_offload_caps_bits csum_cap vlan_cap lro_cap lro_psh_flag lro_time_stamp reserved_at_5 wqe_vlan_insert self_lb_en_modifiable reserved_at_9 max_lso_cap multi_pkt_send_wqe wqe_inline_mode rss_ind_tbl_cap reg_umr_sq scatter_fcs enhanced_multi_pkt_send_wqe tunnel_lso_const_out_ip_id tunnel_lro_gre tunnel_lro_vxlan tunnel_stateless_gre tunnel_stateless_vxlan swp_csum swp_lso cqe_checksum_full tunnel_stateless_geneve_tx tunnel_stateless_mpls_over_udp tunnel_stateless_mpls_over_gre tunnel_stateless_vxlan_gpe tunnel_stateless_ipv4_over_vxlan tunnel_stateless_ip_over_ip insert_trailer tunnel_stateless_ip_over_ip_rx tunnel_stateless_ip_over_ip_tx reserved_at_2e max_vxlan_udp_ports swp_csum_l4_partial reserved_at_39 max_geneve_opt_len tunnel_stateless_geneve_rx lro_min_mss_size lro_timer_supported_periods reserved_at_200 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME mlx5_ifc_roce_cap_bits roce_apm sw_r_roce_src_udp_port fl_rc_qp_when_roce_enabled roce_cc_general qp_ooo_transmit_default qp_ts_format l3_type reserved_at_90 roce_version r_roce_dest_udp_port r_roce_max_src_udp_port r_roce_min_src_udp_port reserved_at_e0 roce_address_table_size mlx5_ifc_atomic_caps_bits atomic_req_8B_endianness_mode supported_atomic_req_8B_endianness_mode_1 atomic_operations atomic_size_qp atomic_size_dc MLX5_WQ_TYPE_LINKED_LIST MLX5_WQ_TYPE_CYCLIC MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ MLX5_WQ_END_PAD_MODE_NONE MLX5_WQ_END_PAD_MODE_ALIGN MLX5_CAP_PORT_TYPE_IB MLX5_CAP_PORT_TYPE_ETH mlx5_ifc_cmd_hca_cap_2_bits reserved_at_81 dp_ordering_force reserved_at_89 query_vuid reserved_at_93 umr_log_entity_size_5 max_reformat_insert_size max_reformat_insert_offset max_reformat_remove_size max_reformat_remove_offset migration_multi_load migration_tracking_state multiplane_qp_ud reserved_at_cb migration_in_chunks reserved_at_d1 sf_eq_usage reserved_at_d3 multiplane reserved_at_d9 cross_vhca_object_to_object_supported allowed_object_for_other_vhca_access flow_table_type_2_type reserved_at_1a8 format_select_dw_8_6_ext log_min_mkey_entity_size reserved_at_1b0 reserved_at_220 sw_vhca_id_valid reserved_at_230 reserved_at_240 ts_cqe_metadata_size2wqe_counter reserved_at_250 reserved_at_260 format_select_dw_gtpu_dw_0 format_select_dw_gtpu_dw_1 format_select_dw_gtpu_dw_2 format_select_dw_gtpu_first_ext_dw_0 generate_wqe_type reserved_at_2c0 reserved_at_380 min_mkey_log_entity_size_fixed_buffer ec_vf_vport_base reserved_at_3a0 max_mkey_log_entity_size_mtt max_rqt_vhca_id reserved_at_3c0 reserved_at_3e0 pcc_ifa2 reserved_at_3f1 reserved_at_400 min_mkey_log_entity_size_fixed_buffer_valid reserved_at_402 return_reg_id reserved_at_420 flow_table_hash_type reserved_at_440 max_num_eqs_24b mlx5_ifc_rx_hash_field_select_bits l3_prot_type l4_prot_type selected_fields mlx5_ifc_wq_bits end_padding_mode cd_slave hds_skip_first_sge log2_hds_buf_size reserved_at_24 lwm uar_page dbr_addr hw_counter sw_counter log_wq_stride reserved_at_110 log_wq_pg_sz reserved_at_118 log_wq_sz dbr_umem_valid wq_umem_valid reserved_at_122 log_hairpin_num_packets log_hairpin_data_sz log_wqe_num_of_strides two_byte_shift_en reserved_at_139 log_wqe_stride_size dbr_umem_id wq_umem_id wq_umem_offset headers_mkey shampo_enable reserved_at_1e1 shampo_mode reserved_at_1e4 log_reservation_size reserved_at_1e8 log_max_num_of_packets_per_reservation log_headers_entry_size reserved_at_1f8 log_headers_buffer_entry_num pas mlx5_ifc_rq_num_bits rq_num mlx5_ifc_rq_vhca_bits rq_vhca_id MLX5_QPC_OFFLOAD_TYPE_RNDV MLX5_TIMESTAMP_FORMAT_FREE_RUNNING MLX5_TIMESTAMP_FORMAT_DEFAULT MLX5_TIMESTAMP_FORMAT_REAL_TIME mlx5_ifc_qpc_bits isolate_vl_tc reserved_at_15 req_e2e_credit_mode offload_type reserved_at_1e atomic_like_write_en latency_sensitive reserved_at_26 log_msg_max reserved_at_48 log_rq_size log_rq_stride no_sq log_sq_size retry_mode ts_format reserved_at_5a rlky ulp_stateless_offload_mode counter_set_id log_page_size remote_qpn primary_address_path secondary_address_path log_ack_req_freq reserved_at_384 log_sra_max reserved_at_38b retry_count reserved_at_393 fre cur_rnr_retry cur_retry_count reserved_at_39b next_send_psn log_num_dci_stream_channels cqn_snd log_num_dci_errored_streams deth_sqpn last_acked_psn log_rra_max reserved_at_48b atomic_mode rre rwe rae reserved_at_493 reserved_at_49a dp_ordering_1 cd_slave_receive cd_slave_send cd_master min_rnr_nak next_rcv_psn reserved_at_4c0 reserved_at_4e0 cqn_rcv q_key reserved_at_560 rq_type srqn_rmpn_xrqn rmsn hw_sq_wqebb_counter sw_sq_wqebb_counter hw_rq_counter sw_rq_counter reserved_at_600 reserved_at_620 cgs cs_req cs_res dc_access_key reserved_at_680 reserved_at_684 mlx5_ifc_tisc_bits strict_lag_tx_port_affinity tls_en underlay_qpn reserved_at_160 reserved_at_180 MLX5_TIRC_DISP_TYPE_DIRECT MLX5_TIRC_DISP_TYPE_INDIRECT MLX5_RX_HASH_FN_NONE MLX5_RX_HASH_FN_INVERTED_XOR8 MLX5_RX_HASH_FN_TOEPLITZ MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST mlx5_ifc_tirc_bits disp_type reserved_at_25 lro_timeout_period_usecs packet_merge_mask lro_max_ip_payload_size inline_rqn rx_hash_symmetric reserved_at_101 tunneled_offload_en reserved_at_103 indirect_table rx_hash_fn reserved_at_124 self_lb_block rx_hash_toeplitz_key rx_hash_field_selector_outer rx_hash_field_selector_inner MLX5_SQC_STATE_RST MLX5_SQC_STATE_RDY MLX5_SQC_STATE_ERR mlx5_ifc_sqc_bits flush_in_error_en allow_multi_pkt_send_wqe min_wqe_inline_mode reg_umr allow_swp non_wire reserved_at_1c cqn hairpin_peer_rq hairpin_peer_vhca packet_pacing_rate_limit_index tis_lst_sz qos_queue_group_id tis_num_0 __empty_rq_num __empty_rq_vhca rq_vhca mlx5_ifc_rqtc_bits list_q_type reserved_at_a8 rqt_max_size rq_vhca_id_format reserved_at_c1 rqt_actual_size MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP MLX5_RQC_STATE_RST MLX5_RQC_STATE_RDY MLX5_RQC_STATE_ERR mlx5_ifc_rqc_bits delay_drop_en vsd mem_rq_type reserved_at_68 rmpn hairpin_peer_sq shampo_no_match_alignment_granularity shampo_match_criteria_type reservation_timeout mlx5_ifc_dctc_bits reserved_at_73 reserved_at_75 reserved_at_98 srqn_xrqn reserved_at_e8 my_addr_index reserved_at_170 dc_access_key_violation_count reserved_at_1a0 mlx5_ifc_rts2rts_qp_in_bits opt_param_mask qpc reserved_at_800 mlx5_ifc_cqe_error_syndrome_bits hw_error_syndrome hw_syndrome_type vendor_error_syndrome mlx5_ifc_modify_tis_bitmask_bits mlx5_ifc_modify_tis_in_bits mlx5_ifc_modify_sq_in_bits sq_state reserved_at_44 sqn modify_bitmask MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID mlx5_ifc_modify_rq_in_bits rq_state rqn mlx5_ifc_create_tis_in_bits mlx5_ifc_create_tir_out_bits icm_address_63_40 icm_address_39_32 icm_address_31_0 mlx5_ifc_create_tir_in_bits mlx5_ifc_create_sq_in_bits mlx5_ifc_create_rqt_in_bits rqt_context mlx5_ifc_create_rq_in_bits mlx5_ifc_create_qp_out_bits mlx5_ifc_create_qp_in_bits qpc_ext reserved_at_41 input_qpn reserved_at_861 mlx5_ifc_create_dct_out_bits dctn mlx5_ifc_create_dct_in_bits dct_context_entry MLX5_MAX_COMMANDS MLX5_CMD_DATA_BLOCK_SIZE MLX5_PCI_CMD_XPORT MLX5_MKEY_BSF_OCTO_SIZE MLX5_MAX_PSVS MLX5_STAT_RATE_OFFSET MLX5_ADAPTER_PAGE_SHIFT MLX5_ADAPTER_PAGE_SIZE MLX5_BFREGS_PER_UAR MLX5_MAX_UARS MLX5_NON_FP_BFREGS_PER_UAR MLX5_FP_BFREGS_PER_UAR MLX5_MAX_BFREGS MLX5_UARS_IN_PAGE MLX5_NON_FP_BFREGS_IN_PAGE MLX5_MIN_DYN_BFREGS MLX5_MAX_DYN_BFREGS MLX5_EVENT_QUEUE_TYPE_QP MLX5_EVENT_QUEUE_TYPE_RQ MLX5_EVENT_QUEUE_TYPE_SQ MLX5_EVENT_QUEUE_TYPE_DCT mlx5_event MLX5_EVENT_TYPE_NOTIFY_ANY MLX5_EVENT_TYPE_COMP MLX5_EVENT_TYPE_PATH_MIG MLX5_EVENT_TYPE_COMM_EST MLX5_EVENT_TYPE_SQ_DRAINED MLX5_EVENT_TYPE_SRQ_LAST_WQE MLX5_EVENT_TYPE_SRQ_RQ_LIMIT MLX5_EVENT_TYPE_CQ_ERROR MLX5_EVENT_TYPE_WQ_CATAS_ERROR MLX5_EVENT_TYPE_PATH_MIG_FAILED MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR MLX5_EVENT_TYPE_WQ_ACCESS_ERROR MLX5_EVENT_TYPE_SRQ_CATAS_ERROR MLX5_EVENT_TYPE_OBJECT_CHANGE MLX5_EVENT_TYPE_INTERNAL_ERROR MLX5_EVENT_TYPE_PORT_CHANGE MLX5_EVENT_TYPE_GPIO_EVENT MLX5_EVENT_TYPE_PORT_MODULE_EVENT MLX5_EVENT_TYPE_TEMP_WARN_EVENT MLX5_EVENT_TYPE_XRQ_ERROR MLX5_EVENT_TYPE_REMOTE_CONFIG MLX5_EVENT_TYPE_GENERAL_EVENT MLX5_EVENT_TYPE_MONITOR_COUNTER MLX5_EVENT_TYPE_PPS_EVENT MLX5_EVENT_TYPE_DB_BF_CONGESTION MLX5_EVENT_TYPE_STALL_EVENT MLX5_EVENT_TYPE_CMD MLX5_EVENT_TYPE_PAGE_REQUEST MLX5_EVENT_TYPE_PAGE_FAULT MLX5_EVENT_TYPE_NIC_VPORT_CHANGE MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED MLX5_EVENT_TYPE_VHCA_STATE_CHANGE MLX5_EVENT_TYPE_DCT_DRAINED MLX5_EVENT_TYPE_DCT_KEY_VIOLATION MLX5_EVENT_TYPE_FPGA_ERROR MLX5_EVENT_TYPE_FPGA_QP_ERROR MLX5_EVENT_TYPE_DEVICE_TRACER MLX5_EVENT_TYPE_MAX mlx5_eqe_comp mlx5_eqe_qp_srq qp_srq_n mlx5_eqe_cq_err mlx5_eqe_xrq_err type_xrqn mlx5_eqe_port_state mlx5_eqe_gpio gpio_event mlx5_eqe_congestion congestion_level mlx5_eqe_stall_vl port_vl mlx5_eqe_cmd mlx5_eqe_page_req ec_function bytes_committed wqe_index pftype_wq r_key rdma_op_len rdma_va pftype_token post_demand_fault_pages pre_demand_fault_pages token47_32 token31_0 demand_fault_pages rdma mlx5_eqe_page_fault mlx5_eqe_vport_change vport_num mlx5_eqe_port_module module_status time_sec time_nsec mlx5_eqe_pps mlx5_eqe_dct mlx5_eqe_temp_warning sensor_warning_msb sensor_warning_lsb mlx5_eqe_obj_change mlx5_eqe_sync_fw_update sync_rst_state mlx5_eqe_vhca_state ev_data qp_srq cq_err stall_vl req_pages vport_change port_module temp_warning xrq_err sync_fw_update obj_change mlx5_eqe MLX5_L3_PROT_TYPE_IPV4 MLX5_L3_PROT_TYPE_IPV6 MLX5_L4_PROT_TYPE_TCP MLX5_L4_PROT_TYPE_UDP MLX5_HASH_FIELD_SEL_SRC_IP MLX5_HASH_FIELD_SEL_DST_IP MLX5_HASH_FIELD_SEL_L4_SPORT MLX5_HASH_FIELD_SEL_L4_DPORT MLX5_HASH_FIELD_SEL_IPSEC_SPI mlx5_mcam_reg_groups MLX5_MCAM_REGS_FIRST_128 MLX5_MCAM_REGS_0x9100_0x917F MLX5_MCAM_REGS_0x9180_0x91FF MLX5_MCAM_REGS_NUM MLX5_BOARD_ID_LEN MLX5_CMD_WQ_MAX_NAME MLX5_MAX_PORTS MLX5_ATOMIC_MODE_OFFSET MLX5_ATOMIC_MODE_IB_COMP MLX5_ATOMIC_MODE_CX MLX5_ATOMIC_MODE_8B MLX5_ATOMIC_MODE_16B MLX5_ATOMIC_MODE_32B MLX5_ATOMIC_MODE_64B MLX5_ATOMIC_MODE_128B MLX5_ATOMIC_MODE_256B MLX5_ATOMIC_OPS_CMP_SWAP MLX5_ATOMIC_OPS_FETCH_ADD MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD dbg_rsc_type MLX5_DBG_RSC_QP MLX5_DBG_RSC_EQ MLX5_DBG_RSC_CQ mlx5_field_desc mlx5_rsc_debug MLX5_NUM_COMMAND_CACHES mlx5_buf_list mlx5_frag_buf mlx5_frag_buf_ctrl sz_m1 frag_sz_m1 strides_offset log_frag_strides mlx5_res_type MLX5_RES_QP MLX5_RES_RQ MLX5_RES_SQ MLX5_RES_SRQ MLX5_RES_XSRQ MLX5_RES_XRQ mlx5_core_rsc_common mlx5_rate_limit max_burst_sz typical_pkt_sz mlx5_func_type MLX5_PF MLX5_VF MLX5_SF MLX5_HOST_PF MLX5_EC_VF MLX5_FUNC_TYPE_NUM MKEY_CACHE_LAST_STD_ENTRY MLX5_IMR_KSM_CACHE_ENTRY MAX_MKEY_CACHE_ENTRIES pgdir mlx5_db_pgdir mlx5_ib_user_db_page mlx5_db mlx5_flow_namespace_type MLX5_FLOW_NAMESPACE_BYPASS MLX5_FLOW_NAMESPACE_KERNEL_RX_MACSEC MLX5_FLOW_NAMESPACE_LAG MLX5_FLOW_NAMESPACE_OFFLOADS MLX5_FLOW_NAMESPACE_ETHTOOL MLX5_FLOW_NAMESPACE_KERNEL MLX5_FLOW_NAMESPACE_LEFTOVERS MLX5_FLOW_NAMESPACE_ANCHOR MLX5_FLOW_NAMESPACE_FDB_BYPASS MLX5_FLOW_NAMESPACE_FDB MLX5_FLOW_NAMESPACE_ESW_EGRESS MLX5_FLOW_NAMESPACE_ESW_INGRESS MLX5_FLOW_NAMESPACE_SNIFFER_RX MLX5_FLOW_NAMESPACE_SNIFFER_TX MLX5_FLOW_NAMESPACE_EGRESS MLX5_FLOW_NAMESPACE_EGRESS_IPSEC MLX5_FLOW_NAMESPACE_EGRESS_MACSEC MLX5_FLOW_NAMESPACE_RDMA_RX MLX5_FLOW_NAMESPACE_RDMA_RX_KERNEL MLX5_FLOW_NAMESPACE_RDMA_TX MLX5_FLOW_NAMESPACE_PORT_SEL MLX5_FLOW_NAMESPACE_RDMA_RX_COUNTERS MLX5_FLOW_NAMESPACE_RDMA_TX_COUNTERS MLX5_FLOW_NAMESPACE_RDMA_RX_IPSEC MLX5_FLOW_NAMESPACE_RDMA_TX_IPSEC MLX5_FLOW_NAMESPACE_RDMA_RX_MACSEC MLX5_FLOW_NAMESPACE_RDMA_TX_MACSEC IB_MGMT_MAD_HDR IB_MGMT_MAD_DATA IB_MGMT_RMPP_HDR IB_MGMT_RMPP_DATA IB_MGMT_VENDOR_HDR IB_MGMT_VENDOR_DATA IB_MGMT_SA_HDR IB_MGMT_SA_DATA IB_MGMT_DEVICE_HDR IB_MGMT_DEVICE_DATA IB_MGMT_MAD_SIZE OPA_MGMT_MAD_DATA OPA_MGMT_RMPP_DATA OPA_MGMT_MAD_SIZE mlx5_core_cq cqe_sz set_ci_db arm_db irqn cons_index arm_sn tasklet_ctx reset_notify_added reset_notify mlx5_eq_comp mlx5_qp_optpar MLX5_QP_OPTPAR_ALT_ADDR_PATH MLX5_QP_OPTPAR_RRE MLX5_QP_OPTPAR_RAE MLX5_QP_OPTPAR_RWE MLX5_QP_OPTPAR_PKEY_INDEX MLX5_QP_OPTPAR_Q_KEY MLX5_QP_OPTPAR_RNR_TIMEOUT MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH MLX5_QP_OPTPAR_SRA_MAX MLX5_QP_OPTPAR_RRA_MAX MLX5_QP_OPTPAR_PM_STATE MLX5_QP_OPTPAR_RETRY_COUNT MLX5_QP_OPTPAR_RNR_RETRY MLX5_QP_OPTPAR_ACK_TIMEOUT MLX5_QP_OPTPAR_LAG_TX_AFF MLX5_QP_OPTPAR_PRI_PORT MLX5_QP_OPTPAR_SRQN MLX5_QP_OPTPAR_CQN_RCV MLX5_QP_OPTPAR_DC_HS MLX5_QP_OPTPAR_DC_KEY MLX5_QP_OPTPAR_COUNTER_SET_ID mlx5_qp_state MLX5_QP_STATE_RST MLX5_QP_STATE_INIT MLX5_QP_STATE_RTR MLX5_QP_STATE_RTS MLX5_QP_STATE_SQER MLX5_QP_STATE_SQD MLX5_QP_STATE_ERR MLX5_QP_STATE_SQ_DRAINING MLX5_QP_STATE_SUSPENDED MLX5_QP_NUM_STATE MLX5_QP_STATE MLX5_QP_STATE_BAD MLX5_SQ_STATE_NA MLX5_SQ_NUM_STATE MLX5_RQ_STATE_NA MLX5_RQ_NUM_STATE MLX5_QP_ST_RC MLX5_QP_ST_UC MLX5_QP_ST_UD MLX5_QP_ST_XRC MLX5_QP_ST_MLX MLX5_QP_ST_DCI MLX5_QP_ST_DCT MLX5_QP_ST_QP0 MLX5_QP_ST_QP1 MLX5_QP_ST_RAW_ETHERTYPE MLX5_QP_ST_RAW_IPV6 MLX5_QP_ST_SNIFFER MLX5_QP_ST_SYNC_UMR MLX5_QP_ST_PTP_1588 MLX5_QP_ST_REG_UMR MLX5_QP_ST_MAX MLX5_QP_PM_MIGRATED MLX5_QP_PM_ARMED MLX5_QP_PM_REARM MLX5_NON_ZERO_RQ MLX5_SRQ_RQ MLX5_CRQ_RQ MLX5_ZERO_LEN_RQ MLX5_WQE_CTRL_CQ_UPDATE MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE MLX5_WQE_CTRL_SOLICITED MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE MLX5_SEND_WQE_DS MLX5_SEND_WQE_BB MLX5_RCV_DBR MLX5_SND_DBR general_id umr_mkey tis_tir_num fm_ce_se mlx5_wqe_ctrl_seg opmod_idx_opcode qpn_ds mlx5_core_qp mlx5_core_dct mqp drained MLX5_QP_FLAG_SIGNATURE MLX5_QP_FLAG_SCATTER_CQE MLX5_QP_FLAG_TUNNEL_OFFLOADS MLX5_QP_FLAG_BFREG_INDEX MLX5_QP_FLAG_TYPE_DCT MLX5_QP_FLAG_TYPE_DCI MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC MLX5_QP_FLAG_ALLOW_SCATTER_CQE MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE MLX5_QP_FLAG_UAR_PAGE_INDEX MLX5_QP_FLAG_DCI_STREAM MLX5_WQ_FLAG_SIGNATURE mlx5_ib_create_qp_dci_streams log_num_concurent log_num_errored sq_buf_addr access_key mlx5_ib_create_qp db_addr sq_wqe_count rq_wqe_count rq_wqe_shift uidx bfreg_index ece_options dci_streams mlx5_rx_hash_function_flags MLX5_RX_HASH_FUNC_TOEPLITZ mlx5_rx_hash_fields MLX5_RX_HASH_SRC_IPV4 MLX5_RX_HASH_DST_IPV4 MLX5_RX_HASH_SRC_IPV6 MLX5_RX_HASH_DST_IPV6 MLX5_RX_HASH_SRC_PORT_TCP MLX5_RX_HASH_DST_PORT_TCP MLX5_RX_HASH_SRC_PORT_UDP MLX5_RX_HASH_DST_PORT_UDP MLX5_RX_HASH_IPSEC_SPI MLX5_RX_HASH_INNER mlx5_ib_create_qp_rss rx_hash_fields_mask rx_hash_function rx_key_len rx_hash_key comp_mask mlx5_ib_create_qp_resp_mask MLX5_IB_CREATE_QP_RESP_MASK_TIRN MLX5_IB_CREATE_QP_RESP_MASK_TISN MLX5_IB_CREATE_QP_RESP_MASK_RQN MLX5_IB_CREATE_QP_RESP_MASK_SQN MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR mlx5_ib_create_qp_resp tir_icm_addr mlx5_ib_create_wq_mask MLX5_IB_CREATE_WQ_STRIDING_RQ mlx5_ib_create_wq single_stride_log_num_of_bytes single_wqe_log_num_of_strides mlx5_ib_burst_info mlx5_ib_modify_qp_mask MLX5_IB_MODIFY_QP_OOO_DP mlx5_ib_modify_qp burst_info mlx5_ib_modify_qp_resp mlx5_ib_create_wq_resp mlx5_ib_create_rwq_ind_tbl_resp mlx5_ib_modify_wq UVERBS_ID_DRIVER_NS UVERBS_ATTR_UHW_IN UVERBS_ATTR_UHW_OUT UVERBS_ID_DRIVER_NS_WITH_UHW uverbs_attrs_create_flow_action_esp UVERBS_ATTR_CREATE_FLOW_ACTION_ESP_HANDLE UVERBS_ATTR_FLOW_ACTION_ESP_ATTRS UVERBS_ATTR_FLOW_ACTION_ESP_ESN UVERBS_ATTR_FLOW_ACTION_ESP_KEYMAT UVERBS_ATTR_FLOW_ACTION_ESP_REPLAY UVERBS_ATTR_FLOW_ACTION_ESP_ENCAP uapi_radix_data UVERBS_API_NS_FLAG UVERBS_API_ATTR_KEY_BITS UVERBS_API_ATTR_KEY_MASK UVERBS_API_ATTR_BKEY_LEN UVERBS_API_WRITE_KEY_NUM UVERBS_API_METHOD_KEY_BITS UVERBS_API_METHOD_KEY_SHIFT UVERBS_API_METHOD_KEY_NUM_CORE UVERBS_API_METHOD_IS_WRITE UVERBS_API_METHOD_IS_WRITE_EX UVERBS_API_METHOD_KEY_NUM_DRIVER UVERBS_API_METHOD_KEY_MASK UVERBS_API_OBJ_KEY_BITS UVERBS_API_OBJ_KEY_SHIFT UVERBS_API_OBJ_KEY_NUM_CORE UVERBS_API_OBJ_KEY_NUM_DRIVER UVERBS_API_OBJ_KEY_MASK UVERBS_API_KEY_ERR mlx5_core_srq srqn max_gs max_avail_gather wqe_shift MLX5_RES_SCAT_DATA32_CQE MLX5_RES_SCAT_DATA64_CQE MLX5_REQ_SCAT_DATA32_CQE MLX5_REQ_SCAT_DATA64_CQE MLX5_CQE_VERSION_V0 MLX5_CQE_VERSION_V1 MLX5_IB_INVALID_UAR_INDEX MLX5_IB_INVALID_BFREG MLX5_MAX_MEMIC_PAGES MLX5_MEMIC_ALLOC_SIZE_MASK mlx5_bfreg_info sys_pages num_low_latency_bfregs lib_uar_4k lib_uar_dyn num_sys_pages num_static_sys_pages total_num_bfregs num_dyn_bfregs mlx5_ib_ucontext ibucontext db_page_list db_page_mutex bfregi lib_caps devx_uid mlx5_ib_pd ibpd mlx5_ib_optional_counter_type MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS MLX5_IB_OPCOUNTER_MAX wr_list mlx5_ib_rq_flags MLX5_IB_RQ_CVLAN_STRIPPING MLX5_IB_RQ_PCI_WRITE_END_PADDING mlx5_ib_wq wrid wr_data w_list wqe_head unsig_count max_post cur_post last_poll cur_edge mlx5_ib_wq_flags MLX5_IB_WQ_FLAGS_DELAY_DROP MLX5_IB_WQ_FLAGS_STRIDING_RQ mlx5_ib_rwq ibwq core_qp rq_num_pas rq_page_offset log_num_strides wqe_count wq_sig mlx5_ib_rwq_ind_table ib_rwq_ind_tbl mlx5_ib_ubuffer mlx5_ib_qp_base container_mibqp mlx5_ib_qp ibqp sq_signal_bits next_fence is_rss is_ooo_rq bfregn qps_list cq_recv_list cq_send_list flags_en counter_pending gsi_lag_port mlx5_ib_qp_trans xrcdn alt_port atomic_rd_en resp_depth mlx5_ib_rss_qp mlx5_ib_rq mlx5_ib_sq mlx5_ib_raw_packet_qp mlx5_bf mlx5_ib_dct mdct trans_qp raw_packet_qp rss_qp mlx5_ib_cq_buf frag_buf nent mlx5_ib_cq_pr_flags MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS mlx5_ib_cq ibcq mcq resize_mutex resize_buf resize_umem list_send_qp list_recv_qp wc_list notify_flags private_flags mlx5_ib_srq ibsrq msrq wqe_ctr mlx5_ib_xrcd ibxrcd rep_data vlan_refcount esw mlx5_ib_dbg_cc_types MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI MLX5_IB_DBG_CC_RP_TIME_RESET MLX5_IB_DBG_CC_RP_BYTE_RESET MLX5_IB_DBG_CC_RP_THRESHOLD MLX5_IB_DBG_CC_RP_AI_RATE MLX5_IB_DBG_CC_RP_MAX_RATE MLX5_IB_DBG_CC_RP_HAI_RATE MLX5_IB_DBG_CC_RP_MIN_DEC_FAC MLX5_IB_DBG_CC_RP_MIN_RATE MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP MLX5_IB_DBG_CC_RP_DCE_TCP_G MLX5_IB_DBG_CC_RP_DCE_TCP_RTT MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE MLX5_IB_DBG_CC_RP_GD MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS MLX5_IB_DBG_CC_NP_CNP_DSCP MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE MLX5_IB_DBG_CC_NP_CNP_PRIO MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP MLX5_IB_DBG_CC_MAX mlx5_ib_stages MLX5_IB_STAGE_INIT MLX5_IB_STAGE_FS MLX5_IB_STAGE_CAPS MLX5_IB_STAGE_NON_DEFAULT_CB MLX5_IB_STAGE_ROCE MLX5_IB_STAGE_QP MLX5_IB_STAGE_SRQ MLX5_IB_STAGE_DEVICE_RESOURCES MLX5_IB_STAGE_ODP MLX5_IB_STAGE_COUNTERS MLX5_IB_STAGE_CONG_DEBUGFS MLX5_IB_STAGE_UAR MLX5_IB_STAGE_BFREG MLX5_IB_STAGE_PRE_IB_REG_UMR MLX5_IB_STAGE_WHITELIST_UID MLX5_IB_STAGE_IB_REG MLX5_IB_STAGE_DEVICE_NOTIFIER MLX5_IB_STAGE_POST_IB_REG_UMR MLX5_IB_STAGE_DELAY_DROP MLX5_IB_STAGE_RESTRACK MLX5_IB_STAGE_MAX REP_ETH REP_IB NUM_REP_TYPES mlx5_eswitch_rep_data MLX5_IB_SQ_UMR_INLINE_THRESHOLD MLX5_IB_ACK_REQ_FREQ raw_qp_set_mask_map MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID MLX5_RAW_QP_RATE_LIMIT MLX5_QP_RM_GO_BACK_N mlx5_modify_raw_qp_param rq_q_ctr_id mlx5_ib_qp_event_work NUM_NON_BLUE_FLAME_BFREGS mlx5_create_qp_params ucmd_size is_rss_raw MLX5_PATH_FLAG_FL MLX5_PATH_FLAG_FREE_AR MLX5_PATH_FLAG_COUNTER mlx5_ib_drain_cqe mlx5_flow_namespace MLX5_XRC_SRQC_STATE_GOOD MLX5_XRC_SRQC_STATE_ERROR mlx5_ifc_xrc_srqc_bits log_xrc_srq_size cont_srq reserved_at_22 reserved_at_46 user_index_equal_xrc_srqn db_record_addr_h db_record_addr_l reserved_at_17e MLX5_SRQC_STATE_GOOD MLX5_SRQC_STATE_ERROR mlx5_ifc_srqc_bits log_srq_size reserved_at_88 MLX5_RMPC_STATE_RDY MLX5_RMPC_STATE_ERR mlx5_ifc_rmpc_bits MLX5_XRQC_STATE_GOOD MLX5_XRQC_STATE_ERROR MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY MLX5_XRQC_TOPOLOGY_TAG_MATCHING MLX5_XRQC_OFFLOAD_RNDV mlx5_ifc_tag_matching_topology_context_bits log_matching_list_sz append_next_index sw_phase_cnt hw_phase_cnt mlx5_ifc_xrqc_bits rlkey reserved_at_18 tag_matching_topology_context mlx5_ifc_query_xrq_in_bits xrqn mlx5_ifc_query_xrc_srq_in_bits xrc_srqn mlx5_ifc_query_srq_in_bits mlx5_ifc_query_rmp_in_bits mlx5_ifc_rmp_bitmask_bits mlx5_ifc_modify_rmp_in_bits mlx5_ifc_destroy_xrq_in_bits mlx5_ifc_destroy_xrc_srq_in_bits mlx5_ifc_destroy_srq_in_bits mlx5_ifc_destroy_rmp_in_bits mlx5_ifc_create_xrq_out_bits mlx5_ifc_create_xrq_in_bits xrq_context mlx5_ifc_create_xrc_srq_out_bits mlx5_ifc_create_xrc_srq_in_bits xrc_srq_context_entry xrc_srq_umem_valid reserved_at_2e1 mlx5_ifc_create_srq_out_bits mlx5_ifc_create_srq_in_bits srq_context_entry mlx5_ifc_create_rmp_out_bits mlx5_ifc_create_rmp_in_bits MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ mlx5_ifc_arm_xrc_srq_in_bits MLX5_ARM_RQ_IN_OP_MOD_SRQ MLX5_ARM_RQ_IN_OP_MOD_XRQ mlx5_ifc_arm_rq_in_bits srq_number MLX5_SRQ_FLAG_ERR MLX5_SRQ_FLAG_WQ_SIG MLX5_SRQ_FLAG_RNDV mlx5_srq_attr db_record tm_log_list_size tm_next_tag tm_hw_phase_cnt tm_sw_phase_cnt ib_odp_counters faults_handled invalidations invalidations_handled ib_block_iter __sg __dma_addr __sg_numblocks __sg_nents __sg_advance __pg_bit ib_umem_odp pfn_list dma_list umem_mutex is_implicit_odp mlx5_ifc_mkc_bits access_mode_4_2 reserved_at_6 reserved_at_e small_fence_on_rdma_read_response umr_en access_mode_1_0 ma_translation_mode mkey_7_0 length64 bsf_en sync_umr reserved_at_63 expected_sigerr_count en_rinval bsf_octword_size crossing_target_vhca_id reserved_at_190 translations_octword_size reserved_at_1e0 MLX5_MKEY_MASK_LEN MLX5_MKEY_MASK_PAGE_SIZE MLX5_MKEY_MASK_START_ADDR MLX5_MKEY_MASK_PD MLX5_MKEY_MASK_EN_RINVAL MLX5_MKEY_MASK_EN_SIGERR MLX5_MKEY_MASK_BSF_EN MLX5_MKEY_MASK_KEY MLX5_MKEY_MASK_QPN MLX5_MKEY_MASK_LR MLX5_MKEY_MASK_LW MLX5_MKEY_MASK_RR MLX5_MKEY_MASK_RW MLX5_MKEY_MASK_A MLX5_MKEY_MASK_SMALL_FENCE MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE MLX5_MKEY_MASK_FREE MLX5_MKEY_MASK_RELAXED_ORDERING_READ MLX5_UMR_TRANSLATION_OFFSET_EN MLX5_UMR_CHECK_NOT_FREE MLX5_UMR_CHECK_FREE MLX5_UMR_INLINE MLX5_OPCODE_NOP MLX5_OPCODE_SEND_INVAL MLX5_OPCODE_RDMA_WRITE MLX5_OPCODE_RDMA_WRITE_IMM MLX5_OPCODE_SEND MLX5_OPCODE_SEND_IMM MLX5_OPCODE_LSO MLX5_OPCODE_RDMA_READ MLX5_OPCODE_ATOMIC_CS MLX5_OPCODE_ATOMIC_FA MLX5_OPCODE_ATOMIC_MASKED_CS MLX5_OPCODE_ATOMIC_MASKED_FA MLX5_OPCODE_BIND_MW MLX5_OPCODE_CONFIG_CMD MLX5_OPCODE_ENHANCED_MPSW MLX5_RECV_OPCODE_RDMA_WRITE_IMM MLX5_RECV_OPCODE_SEND MLX5_RECV_OPCODE_SEND_IMM MLX5_RECV_OPCODE_SEND_INVAL MLX5_CQE_OPCODE_ERROR MLX5_CQE_OPCODE_RESIZE MLX5_OPCODE_SET_PSV MLX5_OPCODE_GET_PSV MLX5_OPCODE_CHECK_PSV MLX5_OPCODE_DUMP MLX5_OPCODE_RGET_PSV MLX5_OPCODE_RCHECK_PSV MLX5_OPCODE_UMR MLX5_OPCODE_FLOW_TBL_ACCESS MLX5_OPCODE_ACCESS_ASO mlx5_mkey_seg pcie_control qpn_mkey7_0 flags_pd bsfs_octo_size xlt_oct_size log2_page_size psv_layout mlx5_core_psv psv_idx psv mlx5_core_sig_ctx psv_memory psv_wire err_item sig_status_checked sig_err_exists sigerr_count MLX5_FENCE_MODE_NONE MLX5_FENCE_MODE_INITIATOR_SMALL MLX5_FENCE_MODE_FENCE MLX5_FENCE_MODE_STRONG_ORDERING MLX5_FENCE_MODE_SMALL_AND_FENCE mlx5_wqe_data_seg xlt_offset bsf_octowords mlx5_wqe_umr_ctrl_seg xlt_octowords mkey_mask xlt_offset_47_16 mlx5_mtt ptag mlx5_ksm mlx5_ib_mtt_access_flags MLX5_IB_MTT_READ MLX5_IB_MTT_WRITE mlx5_mkey_type MLX5_MKEY_MR MLX5_MKEY_MW MLX5_MKEY_INDIRECT_DEVX MLX5_MKEY_NULL MLX5_MKEY_IMPLICIT_CHILD mlx5r_cache_rb_key mlx5_ib_mkey usecount rb_key cache_ent cacheable mlx5_cache_ent mkeys_queue is_tmp fill_to_high_water tmp_cleanup_scheduled descs_alloc desc_map max_descs pi_mr klm_mr mtt_mr data_iova pi_iova meta_ndescs mlx5_ib_mr ibmr mmkey implicit_children odp_destroy odp_stats is_odp_implicit dd_crossed_mr dd_node null_mmkey mlx5_ib_umr_context MLX5_UMR_STATE_UNINIT MLX5_UMR_STATE_ACTIVE MLX5_UMR_STATE_RECOVER MLX5_UMR_STATE_ERR mlx5_mkeys_queue pages_list mlx5r_umr_context mlx5r_umr_wqe ctrl_seg mkey_seg data_seg MAX_UMR_WR MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD MLX5_FT_NIC_RX_2_NIC_RX_RDMA MLX5_FT_NIC_TX_RDMA_2_NIC_TX mlx5_ifc_macsec_cap_bits macsec_epn macsec_crypto_esp_aes_gcm_256_encrypt macsec_crypto_esp_aes_gcm_128_encrypt macsec_crypto_esp_aes_gcm_256_decrypt macsec_crypto_esp_aes_gcm_128_decrypt log_max_macsec_offload min_log_macsec_full_replay_window max_log_macsec_full_replay_window mlx5_driver_event MLX5_DRIVER_EVENT_TYPE_TRAP MLX5_DRIVER_EVENT_UPLINK_NETDEV MLX5_DRIVER_EVENT_MACSEC_SA_ADDED MLX5_DRIVER_EVENT_MACSEC_SA_DELETED MLX5_DRIVER_EVENT_SF_PEER_DEVLINK MLX5_DRIVER_EVENT_AFFILIATION_DONE MLX5_DRIVER_EVENT_AFFILIATION_REMOVED MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE macsec_index physical_gid mlx5_macsec_event_data macdev fs_id mlx5_roce_gids roce_gid_list_entry gid_idx mlx5_macsec_device macsec_devices_list_entry macsec_roce_gids tx_rules_list rx_rules_list uverbs_obj_idr_type destroy_object uverbs_attr_type UVERBS_ATTR_TYPE_NA UVERBS_ATTR_TYPE_PTR_IN UVERBS_ATTR_TYPE_PTR_OUT UVERBS_ATTR_TYPE_IDR UVERBS_ATTR_TYPE_FD UVERBS_ATTR_TYPE_RAW_FD UVERBS_ATTR_TYPE_ENUM_IN UVERBS_ATTR_TYPE_IDRS_ARRAY uverbs_obj_access UVERBS_ACCESS_READ UVERBS_ACCESS_WRITE UVERBS_ACCESS_NEW UVERBS_ACCESS_DESTROY uapi_definition_kind UAPI_DEF_END UAPI_DEF_OBJECT_START UAPI_DEF_WRITE UAPI_DEF_CHAIN_OBJ_TREE UAPI_DEF_CHAIN UAPI_DEF_IS_SUPPORTED_FUNC UAPI_DEF_IS_SUPPORTED_DEV_FN uapi_definition_scope UAPI_SCOPE_OBJECT UAPI_SCOPE_METHOD mlx5_ib_pp_obj_methods MLX5_IB_METHOD_PP_OBJ_ALLOC MLX5_IB_METHOD_PP_OBJ_DESTROY mlx5_ib_pp_alloc_attrs MLX5_IB_ATTR_PP_OBJ_ALLOC_HANDLE MLX5_IB_ATTR_PP_OBJ_ALLOC_CTX MLX5_IB_ATTR_PP_OBJ_ALLOC_FLAGS MLX5_IB_ATTR_PP_OBJ_ALLOC_INDEX mlx5_ib_pp_obj_destroy_attrs MLX5_IB_ATTR_PP_OBJ_DESTROY_HANDLE mlx5_ib_objects MLX5_IB_OBJECT_DEVX MLX5_IB_OBJECT_DEVX_OBJ MLX5_IB_OBJECT_DEVX_UMEM MLX5_IB_OBJECT_FLOW_MATCHER MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD MLX5_IB_OBJECT_VAR MLX5_IB_OBJECT_PP MLX5_IB_OBJECT_UAR MLX5_IB_OBJECT_STEERING_ANCHOR mlx5_ib_uapi_pp_alloc_flags MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX MLX5_SHARED_RESOURCE_UID mlx5_ib_pp dc_key mlx5_av dqp_dct stat_rate_sl fl_mlid rmac grh_gid_fl mlx5_ib_ah ibah xmit_port mlx5_ib_create_ah_resp vuid mlx5_data_direct_registration ib_port_speed IB_SPEED_SDR IB_SPEED_DDR IB_SPEED_QDR IB_SPEED_FDR10 IB_SPEED_FDR IB_SPEED_EDR IB_SPEED_HDR IB_SPEED_NDR IB_SPEED_XDR ib_process_mad_flags IB_MAD_IGNORE_MKEY IB_MAD_IGNORE_BKEY IB_MAD_IGNORE_ALL ib_mad_result IB_MAD_RESULT_FAILURE IB_MAD_RESULT_SUCCESS IB_MAD_RESULT_REPLY IB_MAD_RESULT_CONSUMED mlx5_ifc_phys_layer_cntrs_bits time_since_last_clear_high time_since_last_clear_low symbol_errors_high symbol_errors_low sync_headers_errors_high sync_headers_errors_low edpl_bip_errors_lane0_high edpl_bip_errors_lane0_low edpl_bip_errors_lane1_high edpl_bip_errors_lane1_low edpl_bip_errors_lane2_high edpl_bip_errors_lane2_low edpl_bip_errors_lane3_high edpl_bip_errors_lane3_low fc_fec_corrected_blocks_lane0_high fc_fec_corrected_blocks_lane0_low fc_fec_corrected_blocks_lane1_high fc_fec_corrected_blocks_lane1_low fc_fec_corrected_blocks_lane2_high fc_fec_corrected_blocks_lane2_low fc_fec_corrected_blocks_lane3_high fc_fec_corrected_blocks_lane3_low fc_fec_uncorrectable_blocks_lane0_high fc_fec_uncorrectable_blocks_lane0_low fc_fec_uncorrectable_blocks_lane1_high fc_fec_uncorrectable_blocks_lane1_low fc_fec_uncorrectable_blocks_lane2_high fc_fec_uncorrectable_blocks_lane2_low fc_fec_uncorrectable_blocks_lane3_high fc_fec_uncorrectable_blocks_lane3_low rs_fec_corrected_blocks_high rs_fec_corrected_blocks_low rs_fec_uncorrectable_blocks_high rs_fec_uncorrectable_blocks_low rs_fec_no_errors_blocks_high rs_fec_no_errors_blocks_low rs_fec_single_error_blocks_high rs_fec_single_error_blocks_low rs_fec_corrected_symbols_total_high rs_fec_corrected_symbols_total_low rs_fec_corrected_symbols_lane0_high rs_fec_corrected_symbols_lane0_low rs_fec_corrected_symbols_lane1_high rs_fec_corrected_symbols_lane1_low rs_fec_corrected_symbols_lane2_high rs_fec_corrected_symbols_lane2_low rs_fec_corrected_symbols_lane3_high rs_fec_corrected_symbols_lane3_low successful_recovery_events reserved_at_640 mlx5_ifc_phys_layer_statistical_cntrs_bits phy_received_bits_high phy_received_bits_low phy_symbol_errors_high phy_symbol_errors_low phy_corrected_bits_high phy_corrected_bits_low phy_corrected_bits_lane0_high phy_corrected_bits_lane0_low phy_corrected_bits_lane1_high phy_corrected_bits_lane1_low phy_corrected_bits_lane2_high phy_corrected_bits_lane2_low phy_corrected_bits_lane3_high phy_corrected_bits_lane3_low mlx5_ifc_ib_port_cntrs_grp_data_layout_bits symbol_error_counter link_error_recovery_counter link_downed_counter port_rcv_errors port_rcv_remote_physical_errors port_rcv_switch_relay_errors port_xmit_discards port_xmit_constraint_errors port_rcv_constraint_errors link_overrun_errors vl_15_dropped port_xmit_wait mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits port_xmit_data_high port_xmit_data_low port_rcv_data_high port_rcv_data_low port_xmit_pkts_high port_xmit_pkts_low port_rcv_pkts_high port_rcv_pkts_low port_unicast_xmit_pkts_high port_unicast_xmit_pkts_low port_multicast_xmit_pkts_high port_multicast_xmit_pkts_low port_unicast_rcv_pkts_high port_unicast_rcv_pkts_low port_multicast_rcv_pkts_high port_multicast_rcv_pkts_low mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits transmit_queue_high transmit_queue_low no_buffer_discard_uc_high no_buffer_discard_uc_low mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits wred_discard_high wred_discard_low ecn_marked_tc_high ecn_marked_tc_low mlx5_ifc_eth_per_prio_grp_data_layout_bits rx_octets_high rx_octets_low rx_frames_high rx_frames_low tx_octets_high tx_octets_low tx_frames_high tx_frames_low rx_pause_high rx_pause_low rx_pause_duration_high rx_pause_duration_low tx_pause_high tx_pause_low tx_pause_duration_high tx_pause_duration_low rx_pause_transition_high rx_pause_transition_low rx_discards_high rx_discards_low device_stall_minor_watermark_cnt_high device_stall_minor_watermark_cnt_low device_stall_critical_watermark_cnt_high device_stall_critical_watermark_cnt_low mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits port_transmit_wait_high port_transmit_wait_low rx_buffer_almost_full_high rx_buffer_almost_full_low rx_buffer_full_high rx_buffer_full_low rx_icrc_encapsulated_high rx_icrc_encapsulated_low mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits dot3stats_alignment_errors_high dot3stats_alignment_errors_low dot3stats_fcs_errors_high dot3stats_fcs_errors_low dot3stats_single_collision_frames_high dot3stats_single_collision_frames_low dot3stats_multiple_collision_frames_high dot3stats_multiple_collision_frames_low dot3stats_sqe_test_errors_high dot3stats_sqe_test_errors_low dot3stats_deferred_transmissions_high dot3stats_deferred_transmissions_low dot3stats_late_collisions_high dot3stats_late_collisions_low dot3stats_excessive_collisions_high dot3stats_excessive_collisions_low dot3stats_internal_mac_transmit_errors_high dot3stats_internal_mac_transmit_errors_low dot3stats_carrier_sense_errors_high dot3stats_carrier_sense_errors_low dot3stats_frame_too_longs_high dot3stats_frame_too_longs_low dot3stats_internal_mac_receive_errors_high dot3stats_internal_mac_receive_errors_low dot3stats_symbol_errors_high dot3stats_symbol_errors_low dot3control_in_unknown_opcodes_high dot3control_in_unknown_opcodes_low dot3in_pause_frames_high dot3in_pause_frames_low dot3out_pause_frames_high dot3out_pause_frames_low mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits ether_stats_drop_events_high ether_stats_drop_events_low ether_stats_octets_high ether_stats_octets_low ether_stats_pkts_high ether_stats_pkts_low ether_stats_broadcast_pkts_high ether_stats_broadcast_pkts_low ether_stats_multicast_pkts_high ether_stats_multicast_pkts_low ether_stats_crc_align_errors_high ether_stats_crc_align_errors_low ether_stats_undersize_pkts_high ether_stats_undersize_pkts_low ether_stats_oversize_pkts_high ether_stats_oversize_pkts_low ether_stats_fragments_high ether_stats_fragments_low ether_stats_jabbers_high ether_stats_jabbers_low ether_stats_collisions_high ether_stats_collisions_low ether_stats_pkts64octets_high ether_stats_pkts64octets_low ether_stats_pkts65to127octets_high ether_stats_pkts65to127octets_low ether_stats_pkts128to255octets_high ether_stats_pkts128to255octets_low ether_stats_pkts256to511octets_high ether_stats_pkts256to511octets_low ether_stats_pkts512to1023octets_high ether_stats_pkts512to1023octets_low ether_stats_pkts1024to1518octets_high ether_stats_pkts1024to1518octets_low ether_stats_pkts1519to2047octets_high ether_stats_pkts1519to2047octets_low ether_stats_pkts2048to4095octets_high ether_stats_pkts2048to4095octets_low ether_stats_pkts4096to8191octets_high ether_stats_pkts4096to8191octets_low ether_stats_pkts8192to10239octets_high ether_stats_pkts8192to10239octets_low reserved_at_540 mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits if_in_octets_high if_in_octets_low if_in_ucast_pkts_high if_in_ucast_pkts_low if_in_discards_high if_in_discards_low if_in_errors_high if_in_errors_low if_in_unknown_protos_high if_in_unknown_protos_low if_out_octets_high if_out_octets_low if_out_ucast_pkts_high if_out_ucast_pkts_low if_out_discards_high if_out_discards_low if_out_errors_high if_out_errors_low if_in_multicast_pkts_high if_in_multicast_pkts_low if_in_broadcast_pkts_high if_in_broadcast_pkts_low if_out_multicast_pkts_high if_out_multicast_pkts_low if_out_broadcast_pkts_high if_out_broadcast_pkts_low reserved_at_340 mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits a_frames_transmitted_ok_high a_frames_transmitted_ok_low a_frames_received_ok_high a_frames_received_ok_low a_frame_check_sequence_errors_high a_frame_check_sequence_errors_low a_alignment_errors_high a_alignment_errors_low a_octets_transmitted_ok_high a_octets_transmitted_ok_low a_octets_received_ok_high a_octets_received_ok_low a_multicast_frames_xmitted_ok_high a_multicast_frames_xmitted_ok_low a_broadcast_frames_xmitted_ok_high a_broadcast_frames_xmitted_ok_low a_multicast_frames_received_ok_high a_multicast_frames_received_ok_low a_broadcast_frames_received_ok_high a_broadcast_frames_received_ok_low a_in_range_length_errors_high a_in_range_length_errors_low a_out_of_range_length_field_high a_out_of_range_length_field_low a_frame_too_long_errors_high a_frame_too_long_errors_low a_symbol_error_during_carrier_high a_symbol_error_during_carrier_low a_mac_control_frames_transmitted_high a_mac_control_frames_transmitted_low a_mac_control_frames_received_high a_mac_control_frames_received_low a_unsupported_opcodes_received_high a_unsupported_opcodes_received_low a_pause_mac_ctrl_frames_received_high a_pause_mac_ctrl_frames_received_low a_pause_mac_ctrl_frames_transmitted_high a_pause_mac_ctrl_frames_transmitted_low mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits eth_802_3_cntrs_grp_data_layout eth_2863_cntrs_grp_data_layout eth_2819_cntrs_grp_data_layout eth_3635_cntrs_grp_data_layout eth_extended_cntrs_grp_data_layout eth_per_prio_grp_data_layout eth_per_tc_prio_grp_data_layout eth_per_tc_congest_prio_grp_data_layout ib_port_cntrs_grp_data_layout ib_ext_port_cntrs_grp_data_layout phys_layer_cntrs phys_layer_statistical_cntrs mlx5_ifc_ppcnt_reg_bits swid pnat reserved_at_12 plane_ind reserved_at_38 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO MLX5_IEEE_802_3_COUNTERS_GROUP MLX5_RFC_2863_COUNTERS_GROUP MLX5_RFC_2819_COUNTERS_GROUP MLX5_RFC_3635_COUNTERS_GROUP MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP MLX5_PER_PRIORITY_COUNTERS_GROUP MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP MLX5_PHYSICAL_LAYER_COUNTERS_GROUP MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP MLX5_INFINIBAND_PORT_COUNTERS_GROUP MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP MLX5_REG_SBPR MLX5_REG_SBCM MLX5_REG_QPTS MLX5_REG_QETCR MLX5_REG_QTCT MLX5_REG_QPDPM MLX5_REG_QCAM MLX5_REG_DCBX_PARAM MLX5_REG_DCBX_APP MLX5_REG_FPGA_CAP MLX5_REG_FPGA_CTRL MLX5_REG_FPGA_ACCESS_REG MLX5_REG_CORE_DUMP MLX5_REG_PCAP MLX5_REG_PMTU MLX5_REG_PTYS MLX5_REG_PAOS MLX5_REG_PFCC MLX5_REG_PPCNT MLX5_REG_PPTB MLX5_REG_PBMC MLX5_REG_PMAOS MLX5_REG_PUDE MLX5_REG_PMPE MLX5_REG_PELC MLX5_REG_PVLC MLX5_REG_PCMR MLX5_REG_PDDR MLX5_REG_PMLP MLX5_REG_PPLM MLX5_REG_PCAM MLX5_REG_NODE_DESC MLX5_REG_HOST_ENDIANNESS MLX5_REG_MTCAP MLX5_REG_MTMP MLX5_REG_MCIA MLX5_REG_MFRL MLX5_REG_MLCR MLX5_REG_MRTC MLX5_REG_MTRC_CAP MLX5_REG_MTRC_CONF MLX5_REG_MTRC_STDB MLX5_REG_MTRC_CTRL MLX5_REG_MPEIN MLX5_REG_MPCNT MLX5_REG_MTPPS MLX5_REG_MTPPSE MLX5_REG_MTUTC MLX5_REG_MPEGC MLX5_REG_MPIR MLX5_REG_MCQS MLX5_REG_MCQI MLX5_REG_MCC MLX5_REG_MCDA MLX5_REG_MCAM MLX5_REG_MSECQ MLX5_REG_MSEES MLX5_REG_MIRC MLX5_REG_MTPTM MLX5_REG_MTCTR MLX5_REG_MRTCQ MLX5_REG_SBCAM MLX5_REG_RESOURCE_DUMP MLX5_REG_NIC_CAP MLX5_REG_DTOR MLX5_REG_VHCA_ICM_CTRL ib_class_port_info capability_mask cap_mask2_resp_time redirect_gid redirect_tcslfl redirect_lid redirect_pkey redirect_qp redirect_qkey trap_gid trap_tcslfl trap_lid trap_pkey trap_hlqp trap_qkey ib_port_capability_mask_bits IB_PORT_SM IB_PORT_NOTICE_SUP IB_PORT_TRAP_SUP IB_PORT_OPT_IPD_SUP IB_PORT_AUTO_MIGR_SUP IB_PORT_SL_MAP_SUP IB_PORT_MKEY_NVRAM IB_PORT_PKEY_NVRAM IB_PORT_LED_INFO_SUP IB_PORT_SM_DISABLED IB_PORT_SYS_IMAGE_GUID_SUP IB_PORT_PKEY_SW_EXT_PORT_TRAP_SUP IB_PORT_EXTENDED_SPEEDS_SUP IB_PORT_CAP_MASK2_SUP IB_PORT_CM_SUP IB_PORT_SNMP_TUNNEL_SUP IB_PORT_REINIT_SUP IB_PORT_DEVICE_MGMT_SUP IB_PORT_VENDOR_CLASS_SUP IB_PORT_DR_NOTICE_SUP IB_PORT_CAP_MASK_NOTICE_SUP IB_PORT_BOOT_MGMT_SUP IB_PORT_LINK_LATENCY_SUP IB_PORT_CLIENT_REG_SUP IB_PORT_OTHER_LOCAL_CHANGES_SUP IB_PORT_LINK_SPEED_WIDTH_TABLE_SUP IB_PORT_VENDOR_SPECIFIC_MADS_TABLE_SUP IB_PORT_MCAST_PKEY_TRAP_SUPPRESSION_SUP IB_PORT_MCAST_FDB_TOP_SUP IB_PORT_HIERARCHY_INFO_SUP ib_port_capability_mask2_bits IB_PORT_SET_NODE_DESC_SUP IB_PORT_EX_PORT_INFO_EX_SUP IB_PORT_VIRT_SUP IB_PORT_SWITCH_PORT_STATE_TABLE_SUP IB_PORT_LINK_WIDTH_2X_SUP IB_PORT_LINK_SPEED_HDR_SUP IB_PORT_LINK_SPEED_NDR_SUP IB_PORT_EXTENDED_SPEEDS2_SUP IB_PORT_LINK_SPEED_XDR_SUP ib_smp hop_ptr hop_cnt dr_slid dr_dlid initial_path return_path ib_pma_portcounters port_select counter_select port_rcv_remphys_errors vl15_dropped port_xmit_data port_rcv_data port_xmit_packets port_rcv_packets ib_pma_portcounters_ext port_unicast_xmit_packets port_unicast_rcv_packets port_multicast_xmit_packets port_multicast_rcv_packets MLX5_IB_VENDOR_CLASS1 MLX5_IB_VENDOR_CLASS2 mlx5_ifc_sqerr2rts_qp_in_bits mlx5_ifc_sqd2rts_qp_in_bits mlx5_ifc_rts2rts_qp_out_bits mlx5_ifc_rtr2rts_qp_out_bits mlx5_ifc_rtr2rts_qp_in_bits mlx5_ifc_rst2init_qp_out_bits mlx5_ifc_rst2init_qp_in_bits mlx5_ifc_query_qp_in_bits mlx5_ifc_query_dct_in_bits mlx5_ifc_qp_2rst_in_bits mlx5_ifc_qp_2err_in_bits mlx5_ifc_init2rtr_qp_out_bits mlx5_ifc_init2rtr_qp_in_bits mlx5_ifc_init2init_qp_out_bits mlx5_ifc_init2init_qp_in_bits mlx5_ifc_drain_dct_in_bits mlx5_ifc_destroy_sq_in_bits mlx5_ifc_destroy_rq_in_bits mlx5_ifc_set_delay_drop_params_in_bits delay_drop_timeout mlx5_ifc_destroy_qp_in_bits mlx5_ifc_destroy_dct_in_bits mlx5_ifc_create_sq_out_bits mbox_info ib_send_flags IB_SEND_FENCE IB_SEND_SIGNALED IB_SEND_SOLICITED IB_SEND_INLINE IB_SEND_IP_CSUM IB_SEND_RESERVED_START IB_SEND_RESERVED_END ib_ud_wr ah remote_qkey ib_reg_wr MLX5_MKC_ACCESS_MODE_PA MLX5_MKC_ACCESS_MODE_MTT MLX5_MKC_ACCESS_MODE_KLMS MLX5_MKC_ACCESS_MODE_KSM MLX5_MKC_ACCESS_MODE_SW_ICM MLX5_MKC_ACCESS_MODE_MEMIC MLX5_MKC_ACCESS_MODE_CROSSING MLX5_EXTENDED_UD_AV MLX5_INLINE_SEG MLX5_PERM_LOCAL_READ MLX5_PERM_LOCAL_WRITE MLX5_PERM_REMOTE_READ MLX5_PERM_REMOTE_WRITE MLX5_PERM_ATOMIC MLX5_PERM_UMR_EN MLX5_MKEY_STATUS_FREE MLX5_MKEY_REMOTE_INVAL MLX5_MKEY_FLAG_SYNC_UMR MLX5_MKEY_BSF_EN MLX5_FLAGS_INLINE MLX5_FLAGS_CHECK_FREE MLX5_ETH_WQE_L3_INNER_CSUM MLX5_ETH_WQE_L4_INNER_CSUM MLX5_ETH_WQE_L3_CSUM MLX5_ETH_WQE_L4_CSUM inline_hdr mlx5_wqe_eth_seg swp_outer_l4_offset swp_outer_l3_offset swp_inner_l4_offset swp_inner_l3_offset cs_flags swp_flags flow_table_metadata mlx5_wqe_xrc_seg mlx5_wqe_datagram_seg mlx5_wqe_raddr_seg mlx5_seg_set_psv psv_num transient_sig mlx5_rwqe_sig mlx5_wqe_inline_seg mlx5_sig_type MLX5_DIF_CRC MLX5_DIF_IPCS mlx5_bsf_inl vld_refresh dif_apptag dif_reftag rp_inv_seed dif_inc_ref_guard_check dif_app_bitmask_check copy_byte_mask bs_selector rsvd_wflags rsvd_mflags mlx5_bsf_basic bsf_size_sbs check_byte_mask w_bfs_psv m_bfs_psv mlx5_bsf_ext t_init_gen_pro_size rsvd_epi_size w_tfs_psv m_tfs_psv mlx5_bsf w_inl m_inl mlx5_klm bcount mlx5_stride_block_entry mlx5_stride_block_ctrl_seg bcount_per_cycle repeat_count mlx5_wqe_eth_pad ib_flow_flags IB_FLOW_ATTR_FLAGS_DONT_TRAP IB_FLOW_ATTR_FLAGS_EGRESS IB_FLOW_ATTR_FLAGS_RESERVED uverbs_default_objects UVERBS_OBJECT_DEVICE UVERBS_OBJECT_PD UVERBS_OBJECT_COMP_CHANNEL UVERBS_OBJECT_CQ UVERBS_OBJECT_QP UVERBS_OBJECT_SRQ UVERBS_OBJECT_AH UVERBS_OBJECT_MR UVERBS_OBJECT_MW UVERBS_OBJECT_FLOW UVERBS_OBJECT_XRCD UVERBS_OBJECT_RWQ_IND_TBL UVERBS_OBJECT_WQ UVERBS_OBJECT_FLOW_ACTION UVERBS_OBJECT_DM UVERBS_OBJECT_COUNTERS UVERBS_OBJECT_ASYNC_EVENT ib_uflow_resources collection_num counters_num ib_uflow_object mlx5_ib_flow_matcher_create_attrs MLX5_IB_ATTR_FLOW_MATCHER_CREATE_HANDLE MLX5_IB_ATTR_FLOW_MATCHER_MATCH_MASK MLX5_IB_ATTR_FLOW_MATCHER_FLOW_TYPE MLX5_IB_ATTR_FLOW_MATCHER_MATCH_CRITERIA MLX5_IB_ATTR_FLOW_MATCHER_FLOW_FLAGS MLX5_IB_ATTR_FLOW_MATCHER_FT_TYPE mlx5_ib_flow_matcher_destroy_attrs MLX5_IB_ATTR_FLOW_MATCHER_DESTROY_HANDLE mlx5_ib_flow_matcher_methods MLX5_IB_METHOD_FLOW_MATCHER_CREATE MLX5_IB_METHOD_FLOW_MATCHER_DESTROY mlx5_ib_flow_steering_anchor_create_attrs MLX5_IB_ATTR_STEERING_ANCHOR_CREATE_HANDLE MLX5_IB_ATTR_STEERING_ANCHOR_FT_TYPE MLX5_IB_ATTR_STEERING_ANCHOR_PRIORITY MLX5_IB_ATTR_STEERING_ANCHOR_FT_ID mlx5_ib_flow_steering_anchor_destroy_attrs MLX5_IB_ATTR_STEERING_ANCHOR_DESTROY_HANDLE mlx5_ib_steering_anchor_methods MLX5_IB_METHOD_STEERING_ANCHOR_CREATE MLX5_IB_METHOD_STEERING_ANCHOR_DESTROY mlx5_ib_match_params match_params mlx5_ib_flow_type MLX5_IB_FLOW_TYPE_NORMAL MLX5_IB_FLOW_TYPE_SNIFFER MLX5_IB_FLOW_TYPE_ALL_DEFAULT MLX5_IB_FLOW_TYPE_MC_DEFAULT mlx5_ib_create_flow_flags MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DEFAULT_MISS MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP mlx5_ib_create_flow_attrs MLX5_IB_ATTR_CREATE_FLOW_HANDLE MLX5_IB_ATTR_CREATE_FLOW_MATCH_VALUE MLX5_IB_ATTR_CREATE_FLOW_DEST_QP MLX5_IB_ATTR_CREATE_FLOW_DEST_DEVX MLX5_IB_ATTR_CREATE_FLOW_MATCHER MLX5_IB_ATTR_CREATE_FLOW_ARR_FLOW_ACTIONS MLX5_IB_ATTR_CREATE_FLOW_TAG MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX_OFFSET MLX5_IB_ATTR_CREATE_FLOW_FLAGS mlx5_ib_flow_methods MLX5_IB_METHOD_CREATE_FLOW MLX5_IB_METHOD_DESTROY_FLOW mlx5_ib_flow_action_methods MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER MLX5_IB_METHOD_FLOW_ACTION_CREATE_PACKET_REFORMAT mlx5_ib_create_flow_action_create_modify_header_attrs MLX5_IB_ATTR_CREATE_MODIFY_HEADER_HANDLE MLX5_IB_ATTR_CREATE_MODIFY_HEADER_ACTIONS_PRM MLX5_IB_ATTR_CREATE_MODIFY_HEADER_FT_TYPE mlx5_ib_create_flow_action_create_packet_reformat_attrs MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_HANDLE MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_TYPE MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_FT_TYPE MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_DATA_BUF mlx5_ib_uapi_flow_table_type MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TX mlx5_ib_uapi_flow_action_packet_reformat_type MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL mlx5_ifc_ipv4_layout_bits mlx5_ifc_ipv6_layout_bits mlx5_ifc_ipv6_simple_layout_bits ipv6_127_96 ipv6_95_64 ipv6_63_32 ipv6_31_0 mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits ipv6_simple_layout ipv6_layout ipv4_layout mlx5_ifc_fte_match_set_lyr_2_4_bits smac_47_16 smac_15_0 dmac_47_16 dmac_15_0 first_prio first_cfi first_vid ip_dscp ip_ecn cvlan_tag svlan_tag ip_version tcp_sport tcp_dport l4_type reserved_at_c2 ipv4_ihl reserved_at_c4 ttl_hoplimit udp_dport src_ipv4_src_ipv6 dst_ipv4_dst_ipv6 mlx5_ifc_nvgre_key_bits mlx5_ifc_gre_key_bits nvgre mlx5_ifc_fte_match_set_misc_bits gre_c_present gre_k_present gre_s_present source_sqn source_eswitch_owner_vhca_id outer_second_cvlan_tag inner_second_cvlan_tag outer_second_svlan_tag inner_second_svlan_tag reserved_at_64 gre_protocol vxlan_vni geneve_vni reserved_at_d8 geneve_oam outer_ipv6_flow_label inner_ipv6_flow_label geneve_opt_len geneve_protocol_type inner_esp_spi mlx5_ifc_fte_match_mpls_bits mpls_exp mpls_s_bos mlx5_ifc_fte_match_set_misc2_bits metadata_reg_a macsec_syndrome ipsec_syndrome reserved_at_1b8 mlx5_ifc_fte_match_set_misc3_bits inner_tcp_seq_num outer_tcp_seq_num inner_tcp_ack_num outer_tcp_ack_num outer_vxlan_gpe_vni outer_vxlan_gpe_next_protocol outer_vxlan_gpe_flags icmp_header_data icmpv6_header_data icmp_type icmp_code icmpv6_type icmpv6_code gtpu_teid gtpu_msg_type gtpu_msg_flags gtpu_dw_2 gtpu_first_ext_dw_0 gtpu_dw_0 mlx5_ifc_fte_match_set_misc4_bits prog_sample_field_value_0 prog_sample_field_id_0 prog_sample_field_value_1 prog_sample_field_id_1 prog_sample_field_value_2 prog_sample_field_id_2 prog_sample_field_value_3 prog_sample_field_id_3 mlx5_ifc_fte_match_set_misc5_bits macsec_tag_0 macsec_tag_1 macsec_tag_2 macsec_tag_3 tunnel_header_0 tunnel_header_1 tunnel_header_2 tunnel_header_3 mlx5_ifc_flow_table_eswitch_cap_bits fdb_to_vport_reg_c_id fdb_uplink_hairpin fdb_multi_path_any_table_limit_regc fdb_dynamic_tunnel fdb_multi_path_any_table fdb_modify_header_fwd_to_table fdb_ipv4_ttl_modify flow_source multi_fdb_encap egress_acl_forward_to_vport fdb_multi_path_to_table reserved_at_1d flow_table_properties_nic_esw_fdb flow_table_properties_esw_acl_ingress flow_table_properties_esw_acl_egress ft_field_support_2_esw_fdb ft_field_bitmask_support_2_esw_fdb reserved_at_1500 sw_steering_fdb_action_drop_icm_address_rx sw_steering_fdb_action_drop_icm_address_tx sw_steering_uplink_icm_address_rx sw_steering_uplink_icm_address_tx reserved_at_1900 mlx5_ifc_fte_match_param_bits outer_headers misc_parameters inner_headers misc_parameters_2 misc_parameters_3 misc_parameters_4 misc_parameters_5 MLX5_FLOW_CONTEXT_ACTION_ALLOW MLX5_FLOW_CONTEXT_ACTION_DROP MLX5_FLOW_CONTEXT_ACTION_FWD_DEST MLX5_FLOW_CONTEXT_ACTION_COUNT MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT MLX5_FLOW_CONTEXT_ACTION_DECAP MLX5_FLOW_CONTEXT_ACTION_MOD_HDR MLX5_FLOW_CONTEXT_ACTION_VLAN_POP MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO mlx5_ifc_general_obj_create_param_bits alias_object log_obj_range mlx5_ifc_general_obj_query_param_bits obj_offset mlx5_ifc_general_obj_in_cmd_hdr_bits vhca_tunnel_id mlx5_reformat_ctx_type MLX5_REFORMAT_TYPE_L2_TO_VXLAN MLX5_REFORMAT_TYPE_L2_TO_NVGRE MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 MLX5_REFORMAT_TYPE_INSERT_HDR MLX5_REFORMAT_TYPE_REMOVE_HDR MLX5_REFORMAT_TYPE_ADD_MACSEC MLX5_REFORMAT_TYPE_DEL_MACSEC mlx5_ifc_destroy_flow_table_in_bits other_vport vport_number table_type mlx5_ifc_dealloc_flow_counter_in_bits flow_counter_id mlx5_ifc_create_flow_group_in_bits source_eswitch_owner_vhca_id_valid start_flow_index end_flow_index match_definer_id match_criteria_enable match_criteria reserved_at_1200 mlx5_mpls_supported_fields MLX5_FIELD_SUPPORT_MPLS_LABEL MLX5_FIELD_SUPPORT_MPLS_EXP MLX5_FIELD_SUPPORT_MPLS_S_BOS MLX5_FIELD_SUPPORT_MPLS_TTL mlx5_flow_destination_type MLX5_FLOW_DESTINATION_TYPE_NONE MLX5_FLOW_DESTINATION_TYPE_VPORT MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE MLX5_FLOW_DESTINATION_TYPE_TIR MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER MLX5_FLOW_DESTINATION_TYPE_UPLINK MLX5_FLOW_DESTINATION_TYPE_PORT MLX5_FLOW_DESTINATION_TYPE_COUNTER MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM MLX5_FLOW_DESTINATION_TYPE_RANGE MLX5_FLOW_DESTINATION_TYPE_TABLE_TYPE MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO MLX5_FLOW_CONTEXT_ACTION_ENCRYPT MLX5_FLOW_CONTEXT_ACTION_DECRYPT MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT MLX5_FLOW_TABLE_TUNNEL_EN_DECAP MLX5_FLOW_TABLE_TERMINATION MLX5_FLOW_TABLE_UNMANAGED MLX5_FLOW_TABLE_OTHER_VPORT MLX5_FLOW_TABLE_UPLINK_VPORT FLOW_CONTEXT_HAS_TAG FLOW_CONTEXT_UPLINK_HAIRPIN_EN mlx5_flow_context mlx5_flow_spec flow_context mlx5_flow_dest_range_field MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN pkt_reformat mlx5_pkt_reformat hit_ft miss_ft tir_num ft_num sampler_id mlx5_flow_destination max_num_groups num_reserved_entries mlx5_flow_table_attr max_fte next_ft meter_idx init_color ctrl_data flow_meter mlx5_exe_aso mlx5_fs_vlan ethtype FLOW_ACT_NO_APPEND FLOW_ACT_IGNORE_FLOW_LEVEL mlx5_flow_act_crypto_params mlx5_flow_act modify_hdr exe_aso mlx5_modify_hdr mlx5_pkt_reformat_params param_0 param_1 MLX5_ESWITCH_LEGACY MLX5_ESWITCH_OFFLOADS mlx5_ib_flow_counters_desc mlx5_ib_flow_counters_data counters_data mlx5_ib_create_flow ncounters_data MLX5_IB_FLOW_ACTION_MODIFY_HEADER MLX5_IB_FLOW_ACTION_PACKET_REFORMAT MLX5_IB_FLOW_ACTION_DECAP mlx5_ib_flow_handler ibflow ibcounters flow_matcher mlx5_ib_flow_matcher matcher_mask mask_len mlx5_ib_steering_anchor ft_prio ib_flags mlx5_accel_esp_xfrm esp_aes_gcm flow_action_raw mlx5_ib_flow_action ib_action mlx5_read_counters_attr hw_cntrs_hndl mlx5_ib_counters_type MLX5_IB_COUNTERS_FLOW mlx5_ib_mcounters ibcntrs cntrs_max_index mcntrs_mutex core_dct core_cq flow_counter_bulk_size devx_obj dinlen dinbox event_sub MATCH_CRITERIA_ENABLE_OUTER_BIT MATCH_CRITERIA_ENABLE_MISC_BIT MATCH_CRITERIA_ENABLE_INNER_BIT MATCH_CRITERIA_ENABLE_MISC2_BIT flow_table_type MLX5_IB_FT_RX MLX5_IB_FT_TX RDMA_RX_ECN_OPCOUNTER_PRIO RDMA_RX_CNP_OPCOUNTER_PRIO RDMA_TX_CNP_OPCOUNTER_PRIO LEFTOVERS_MC LEFTOVERS_UC flow_attr eth_flow _create_flow_rule fs_matcher flow_act dst_num _create_raw_flow_rule mcast _get_flow_table attrs_bundle _uverbs_copy_from field_support check_mpls_supp_fields init_attr create_ib_ah rsc_type create_resource_common ib_attr flow_is_multicast_only flow_matcher_cleanup dest_type get_dests ft_type get_flow_table get_match_criteria_enable handle_local_inv nreq psv_index handle_psv handle_reg_mr_integrity mbox_alloc ignore_mkey ignore_bkey in_wc in_grh in_mad response_mad mlx5_MAD_IFC mlx5_cleanup_qp_table mlx5_core_create_dct mlx5_core_create_rq_tracked mlx5_core_create_sq_tracked mlx5_core_dct_query mlx5_core_destroy_dct mlx5_core_destroy_qp mlx5_core_destroy_rq_tracked mlx5_core_destroy_sq_tracked mlx5_core_put_rsc mlx5_core_qp_modify mlx5_core_qp_query res_num res_type mlx5_core_res_hold mlx5_core_res_put timeout_usec mlx5_core_set_delay_drop mlx5_core_xrcd_alloc mlx5_core_xrcd_dealloc mlx5_data_direct_driver_register mlx5_data_direct_driver_unregister mlx5_data_direct_ib_reg mlx5_data_direct_ib_unreg mlx5_data_direct_probe mlx5_data_direct_remove mlx5_data_direct_shutdown __inl mlx5_fill_inl_bsf rsn mlx5_get_rsc mlx5_ib_create_ah mlx5_ib_destroy_flow mlx5_ib_destroy_flow_action opfc mlx5_ib_fs_add_op_fc mlx5_ib_fs_cleanup_anchor mlx5_ib_fs_init mlx5_ib_fs_remove_op_fc mlx5_ib_handler_MLX5_IB_METHOD_CREATE_FLOW mlx5_ib_handler_MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER mlx5_ib_handler_MLX5_IB_METHOD_FLOW_ACTION_CREATE_PACKET_REFORMAT mlx5_ib_handler_MLX5_IB_METHOD_FLOW_MATCHER_CREATE mlx5_ib_handler_MLX5_IB_METHOD_STEERING_ANCHOR_CREATE bad_wr mlx5_ib_post_recv mlx5_ib_post_send mad_flags out_mad_size out_mad_pkey_index mlx5_ib_process_mad mlx5_ib_query_ah mlx5_ib_shared_ft_allowed mlx5_init_qp_table mlx5_qpc_create_qp mlx5_query_ext_port_caps mlx5_query_mad_ifc_gids mlx5_query_mad_ifc_max_pkeys mlx5_query_mad_ifc_node_desc mlx5_query_mad_ifc_node_guid mlx5_query_mad_ifc_pkey mlx5_query_mad_ifc_port out_mad mlx5_query_mad_ifc_smp_attr_node_info mlx5_query_mad_ifc_system_image_guid mlx5_query_mad_ifc_vendor_id sig_mr bsf mlx5_set_bsf mlx5_steering_anchor_destroy_res send_signaled mlx5r_begin_wqe mlx5_opcode mlx5r_finish_wqe wqe_sz mlx5r_memcpy_send_wqe mlx5r_ring_db mlx5r_wq_overflow modify_qp_mbox_alloc maction is_egress parse_flow_flow_action process_pma_cmd plane_num query_ib_ppcnt raw_fs_rule_add rdma_ah_set_dgid_raw rsc_event_notifier set_data_inl_seg set_datagram_seg set_eth_seg send_wr set_pi_umr_wr outer_c outer_v set_proto check_not_free set_reg_wr set_sig_data_segment set_tos steering_anchor_cleanup steering_anchor_create_res steering_anchor_create_rule_goto_table mlx5_ifc_cong_control_r_roce_ecn_np_bits min_time_between_cnps cnp_dscp cnp_prio_mode cnp_802p_prio mlx5_ifc_cong_control_r_roce_ecn_rp_bits clamp_tgt_rate reserved_at_65 clamp_tgt_rate_after_time_inc reserved_at_69 rate_to_set_on_first_cnp dce_tcp_g dce_tcp_rtt rate_reduce_monitor_period initial_alpha_value mlx5_ifc_cong_control_r_roce_general_bits rtt_resp_dscp_valid rtt_resp_dscp mlx5_ifc_cong_control_802_1qau_rp_bits mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp mlx5_ifc_field_select_802_1qau_rp_bits field_select_8021qaurp mlx5_ifc_cong_control_roce_ecn_auto_bits cong_control_802_1qau_rp cong_control_r_roce_ecn_rp cong_control_r_roce_ecn_np cong_control_r_roce_general mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select_802_1qau_rp mlx5_ifc_modify_cong_params_in_bits field_select congestion_parameters mlx5_ib_cong_node_type MLX5_IB_RROCE_ECN_RP MLX5_IB_RROCE_ECN_NP MLX5_IB_RROCE_GENERAL rdma_network_type RDMA_NETWORK_IB RDMA_NETWORK_ROCE_V1 RDMA_NETWORK_IPV4 RDMA_NETWORK_IPV6 ib_wc_flags IB_WC_GRH IB_WC_WITH_IMM IB_WC_WITH_INVALIDATE IB_WC_IP_CSUM_OK IB_WC_WITH_SMAC IB_WC_WITH_VLAN IB_WC_WITH_NETWORK_HDR_TYPE mlx5_ifc_resize_field_select_bits resize_field_select mlx5_ifc_modify_field_select_bits modify_field_select mlx5_ifc_cqc_bits apu_cq scqe_break_moderation_en oi cqe_comp_en mini_cqe_res_format cqe_compression_layout log_cq_size cq_period cq_max_count c_eqn_or_apu_element reserved_at_c8 last_notified_index last_solicit_index consumer_counter producer_counter mlx5_ifc_modify_field_select_resize_field_select_auto_bits mlx5_ifc_modify_cq_in_bits modify_field_select_resize_field_select cq_umem_valid mlx5_ifc_create_cq_in_bits mlx5_err_cqe vendor_err_synd s_wqe_opcode_qpn wqe_counter op_own tcppsh_abort_dupack tcp_win ack_seq_num header_entry_index lro inval_rkey ft_metadata validity_iteration_count mlx5_cqe64 tls_outer_l3_tunneled wqe_id rss_hash_result rss_hash_type ml_path check_sum flags_rqpn hds_ip_ext l4_l3_hdr_type rsvd40 byte_cnt timestamp_h timestamp_l sop_drop_qpn MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 CQE_L2_OK CQE_L3_OK CQE_L4_OK mlx5_sig_err_cqe expected_trans_sig actual_trans_sig expected_reftag actual_reftag rsvd22 err_offset rsvd30 rsvd38 MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR MLX5_CQE_SYNDROME_LOCAL_PROT_ERR MLX5_CQE_SYNDROME_WR_FLUSH_ERR MLX5_CQE_SYNDROME_MW_BIND_ERR MLX5_CQE_SYNDROME_BAD_RESP_ERR MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR MLX5_CQE_SYNDROME_REMOTE_OP_ERR MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR MLX5_CQE_OWNER_MASK MLX5_CQE_REQ MLX5_CQE_RESP_WR_IMM MLX5_CQE_RESP_SEND MLX5_CQE_RESP_SEND_IMM MLX5_CQE_RESP_SEND_INV MLX5_CQE_RESIZE_CQ MLX5_CQE_SIG_ERR MLX5_CQE_REQ_ERR MLX5_CQE_RESP_ERR MLX5_CQE_INVALID MLX5_CQ_OPMOD_RESIZE MLX5_MODIFY_CQ_MASK_LOG_SIZE MLX5_MODIFY_CQ_MASK_PG_OFFSET MLX5_MODIFY_CQ_MASK_PG_SIZE CQE_STRIDE_64 CQE_STRIDE_128 CQE_STRIDE_128_PAD MLX5_CQ_DB_REQ_NOT_SOL MLX5_CQ_DB_REQ_NOT mlx5_ib_cqe_comp_res_format MLX5_IB_CQE_RES_FORMAT_HASH MLX5_IB_CQE_RES_FORMAT_CSUM MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX mlx5_ib_create_cq_flags MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS mlx5_ib_create_cq cqe_comp_res_format uar_page_index mlx5_ib_resize_cq uverbs_methods_cq UVERBS_METHOD_CQ_CREATE UVERBS_METHOD_CQ_DESTROY mlx5_ib_create_cq_attrs MLX5_IB_ATTR_CREATE_CQ_UAR_INDEX mlx5_ib_wc MLX5_CQE_RES_FORMAT_HASH MLX5_CQE_RES_FORMAT_CSUM MLX5_CQE_RES_FORMAT_CSUM_STRIDX uverbs_methods_dm UVERBS_METHOD_DM_ALLOC UVERBS_METHOD_DM_FREE mlx5_ifc_device_mem_cap_bits memic log_min_memic_alloc_size log_max_memic_addr_alignment memic_bar_start_addr memic_bar_size max_memic_size steering_sw_icm_start_address log_header_modify_sw_icm_size log_sw_icm_alloc_granularity log_steering_sw_icm_size log_indirect_encap_sw_icm_size log_header_modify_pattern_sw_icm_size header_modify_sw_icm_start_address header_modify_pattern_sw_icm_start_address memic_operations indirect_encap_sw_icm_start_address MLX5_MODIFY_MEMIC_OP_MOD_ALLOC MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC mlx5_ifc_modify_memic_in_bits memic_operation_type memic_start_addr mlx5_ifc_alloc_memic_in_bits log_memic_addr_alignment range_start_addr memic_size mlx5_ifc_dealloc_memic_in_bits mlx5_sw_icm_type MLX5_SW_ICM_TYPE_STEERING MLX5_SW_ICM_TYPE_HEADER_MODIFY MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN MLX5_SW_ICM_TYPE_SW_ENCAP mlx5_ib_uapi_dm_type MLX5_IB_UAPI_DM_TYPE_MEMIC MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_PATTERN_SW_ICM MLX5_IB_UAPI_DM_TYPE_ENCAP_SW_ICM mlx5_ib_mmap_cmd MLX5_IB_MMAP_REGULAR_PAGE MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES MLX5_IB_MMAP_WC_PAGE MLX5_IB_MMAP_NC_PAGE MLX5_IB_MMAP_CORE_CLOCK MLX5_IB_MMAP_ALLOC_WC MLX5_IB_MMAP_CLOCK_INFO MLX5_IB_MMAP_DEVICE_MEM mlx5_ib_dm_methods MLX5_IB_METHOD_DM_MAP_OP_ADDR MLX5_IB_METHOD_DM_QUERY mlx5_ib_dm_map_op_addr_attrs MLX5_IB_ATTR_DM_MAP_OP_ADDR_REQ_HANDLE MLX5_IB_ATTR_DM_MAP_OP_ADDR_REQ_OP MLX5_IB_ATTR_DM_MAP_OP_ADDR_RESP_START_OFFSET MLX5_IB_ATTR_DM_MAP_OP_ADDR_RESP_PAGE_INDEX mlx5_ib_query_dm_attrs MLX5_IB_ATTR_QUERY_DM_REQ_HANDLE MLX5_IB_ATTR_QUERY_DM_RESP_START_OFFSET MLX5_IB_ATTR_QUERY_DM_RESP_PAGE_INDEX MLX5_IB_ATTR_QUERY_DM_RESP_LENGTH mlx5_ib_alloc_dm_attrs MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE MLX5_MEMIC_BASE_ALIGN MLX5_MEMIC_BASE_SIZE mlx5_ib_mmap_type MLX5_IB_MMAP_TYPE_MEMIC MLX5_IB_MMAP_TYPE_VAR MLX5_IB_MMAP_TYPE_UAR_WC MLX5_IB_MMAP_TYPE_UAR_NC MLX5_IB_MMAP_TYPE_MEMIC_OP mlx5_user_mmap_entry rdma_entry mmap_flag page_idx mlx5_ib_dm ibdm mlx5_ib_dm_op_entry mentry op_addr mlx5_ib_dm_memic ops_xa_lock mlx5_ib_dm_icm IFLA_VF_LINK_STATE_AUTO IFLA_VF_LINK_STATE_ENABLE IFLA_VF_LINK_STATE_DISABLE __IFLA_VF_LINK_STATE_MAX MLX5_HCA_VPORT_SEL_PORT_GUID MLX5_HCA_VPORT_SEL_NODE_GUID MLX5_HCA_VPORT_SEL_STATE_POLICY phy_port_state MLX5_AAA_111 mlx5_hca_vport_context sm_virt_aware has_raw port_physical_state cap_mask1 cap_mask1_perm cap_mask2 cap_mask2_perm qkey_violation_counter pkey_violation_counter grh_required RDMA_NODE_IB_CA RDMA_NODE_IB_SWITCH RDMA_NODE_IB_ROUTER RDMA_NODE_RNIC RDMA_NODE_USNIC RDMA_NODE_USNIC_UDP RDMA_NODE_UNSPECIFIED ib_signature_prot_cap IB_PROT_T10DIF_TYPE_1 IB_PROT_T10DIF_TYPE_2 IB_PROT_T10DIF_TYPE_3 ib_signature_guard_cap IB_GUARD_T10DIF_CRC IB_GUARD_T10DIF_CSUM ib_device_cap_flags IB_DEVICE_RESIZE_MAX_WR IB_DEVICE_BAD_PKEY_CNTR IB_DEVICE_BAD_QKEY_CNTR IB_DEVICE_RAW_MULTI IB_DEVICE_AUTO_PATH_MIG IB_DEVICE_CHANGE_PHY_PORT IB_DEVICE_UD_AV_PORT_ENFORCE IB_DEVICE_CURR_QP_STATE_MOD IB_DEVICE_SHUTDOWN_PORT IB_DEVICE_PORT_ACTIVE_EVENT IB_DEVICE_SYS_IMAGE_GUID IB_DEVICE_RC_RNR_NAK_GEN IB_DEVICE_SRQ_RESIZE IB_DEVICE_N_NOTIFY_CQ IB_DEVICE_MEM_WINDOW IB_DEVICE_UD_IP_CSUM IB_DEVICE_XRC IB_DEVICE_MEM_MGT_EXTENSIONS IB_DEVICE_MEM_WINDOW_TYPE_2A IB_DEVICE_MEM_WINDOW_TYPE_2B IB_DEVICE_RC_IP_CSUM IB_DEVICE_RAW_IP_CSUM IB_DEVICE_MANAGED_FLOW_STEERING IB_DEVICE_RAW_SCATTER_FCS IB_DEVICE_PCI_WRITE_END_PADDING IB_DEVICE_FLUSH_GLOBAL IB_DEVICE_FLUSH_PERSISTENT IB_DEVICE_ATOMIC_WRITE ib_kernel_cap_flags IBK_LOCAL_DMA_LKEY IBK_INTEGRITY_HANDOVER IBK_ON_DEMAND_PAGING IBK_SG_GAPS_REG IBK_ALLOW_USER_UNREG IBK_BLOCK_MULTICAST_LOOPBACK IBK_UD_TSO IBK_VIRTUAL_FUNCTION IBK_RDMA_NETDEV_OPA ib_odp_general_cap_bits IB_ODP_SUPPORT IB_ODP_SUPPORT_IMPLICIT ib_odp_transport_cap_bits IB_ODP_SUPPORT_SEND IB_ODP_SUPPORT_RECV IB_ODP_SUPPORT_WRITE IB_ODP_SUPPORT_READ IB_ODP_SUPPORT_ATOMIC IB_ODP_SUPPORT_SRQ_RECV ib_tm_cap_flags IB_TM_CAP_RNDV_RC ib_port_phys_state IB_PORT_PHYS_STATE_SLEEP IB_PORT_PHYS_STATE_POLLING IB_PORT_PHYS_STATE_DISABLED IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING IB_PORT_PHYS_STATE_LINK_UP IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY IB_PORT_PHYS_STATE_PHY_TEST ib_port_width IB_WIDTH_1X IB_WIDTH_2X IB_WIDTH_4X IB_WIDTH_8X IB_WIDTH_12X ib_device_modify_flags IB_DEVICE_MODIFY_SYS_IMAGE_GUID IB_DEVICE_MODIFY_NODE_DESC IB_LRH_BYTES IB_ETH_BYTES IB_VLAN_BYTES IB_GRH_BYTES IB_IP4_BYTES IB_UDP_BYTES IB_BTH_BYTES IB_DETH_BYTES IB_EXT_ATOMICETH_BYTES IB_EXT_XRC_BYTES IB_ICRC_BYTES mlx5_ifc_virtio_emulation_cap_bits desc_tunnel_offload_type eth_frame_offload_type virtio_version_1_0 device_features_bits_mask event_mode virtio_queue_type max_tunnel_desc log_doorbell_stride log_doorbell_bar_size doorbell_bar_offset max_emulated_devices max_num_virtio_queues desc_group_mkey_supported freeze_to_rdy_supported reserved_at_d5 umem_1_buffer_param_a umem_1_buffer_param_b umem_2_buffer_param_a umem_2_buffer_param_b umem_3_buffer_param_a umem_3_buffer_param_b MLX5_CAP_UMR_FENCE_STRONG MLX5_CAP_UMR_FENCE_SMALL MLX5_CAP_UMR_FENCE_NONE mlx5_ifc_create_mkey_in_bits pg_access mkey_umem_valid memory_key_mkey_entry translations_octword_actual_size klm_pas_mtt mlx5_ifc_alloc_pd_out_bits mlx5_ifc_alloc_pd_in_bits mlx5_ifc_ptys_reg_bits an_disable_admin an_disable_cap proto_mask an_status data_rate_oper ext_eth_proto_capability eth_proto_capability ib_link_width_capability ib_proto_capability ext_eth_proto_admin eth_proto_admin ib_link_width_admin ib_proto_admin ext_eth_proto_oper eth_proto_oper ib_link_width_oper ib_proto_oper eth_proto_lp_advertise MLX5_MIN_PKEY_TABLE_SIZE MLX5_MAX_LOG_PKEY_TABLE MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT MLX5_PORT_CHANGE_SUBTYPE_DOWN MLX5_PORT_CHANGE_SUBTYPE_ACTIVE MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED MLX5_PORT_CHANGE_SUBTYPE_LID MLX5_PORT_CHANGE_SUBTYPE_PKEY MLX5_PORT_CHANGE_SUBTYPE_GUID MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG MLX5_ROCE_VERSION_1 MLX5_ROCE_VERSION_2 MLX5_ROCE_VERSION_1_CAP MLX5_ROCE_VERSION_2_CAP MLX5_ROCE_L3_TYPE_IPV4 MLX5_ROCE_L3_TYPE_IPV6 MLX5_ROCE_L3_TYPE_IPV4_CAP MLX5_ROCE_L3_TYPE_IPV6_CAP MLX5_MAX_SGE_RD mlx5_dev_event MLX5_DEV_EVENT_SYS_ERROR MLX5_DEV_EVENT_PORT_AFFINITY MLX5_DEV_EVENT_MULTIPORT_ESW MLX5_PTYS_IB MLX5_PTYS_EN mlx5e_link_mode MLX5E_1000BASE_CX_SGMII MLX5E_1000BASE_KX MLX5E_10GBASE_CX4 MLX5E_10GBASE_KX4 MLX5E_10GBASE_KR MLX5E_20GBASE_KR2 MLX5E_40GBASE_CR4 MLX5E_40GBASE_KR4 MLX5E_56GBASE_R4 MLX5E_10GBASE_CR MLX5E_10GBASE_SR MLX5E_10GBASE_ER MLX5E_40GBASE_SR4 MLX5E_40GBASE_LR4 MLX5E_50GBASE_SR2 MLX5E_100GBASE_CR4 MLX5E_100GBASE_SR4 MLX5E_100GBASE_KR4 MLX5E_100GBASE_LR4 MLX5E_100BASE_TX MLX5E_1000BASE_T MLX5E_10GBASE_T MLX5E_25GBASE_CR MLX5E_25GBASE_KR MLX5E_25GBASE_SR MLX5E_50GBASE_CR2 MLX5E_50GBASE_KR2 MLX5E_LINK_MODES_NUMBER mlx5e_ext_link_mode MLX5E_SGMII_100M MLX5E_1000BASE_X_SGMII MLX5E_5GBASE_R MLX5E_10GBASE_XFI_XAUI_1 MLX5E_40GBASE_XLAUI_4_XLPPI_4 MLX5E_25GAUI_1_25GBASE_CR_KR MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR MLX5E_CAUI_4_100GBASE_CR4_KR4 MLX5E_100GAUI_2_100GBASE_CR2_KR2 MLX5E_100GAUI_1_100GBASE_CR_KR MLX5E_200GAUI_4_200GBASE_CR4_KR4 MLX5E_200GAUI_2_200GBASE_CR2_KR2 MLX5E_400GAUI_8_400GBASE_CR8 MLX5E_400GAUI_4_400GBASE_CR4_KR4 MLX5E_800GAUI_8_800GBASE_CR8_KR8 MLX5E_EXT_LINK_MODES_NUMBER mlx5_ptys_width MLX5_PTYS_WIDTH_1X MLX5_PTYS_WIDTH_2X MLX5_PTYS_WIDTH_4X MLX5_PTYS_WIDTH_8X MLX5_PTYS_WIDTH_12X MLX5_VPORT_PF MLX5_VPORT_FIRST_VF MLX5_VPORT_ECPF MLX5_VPORT_UPLINK rdma_lag_flags RDMA_LAG_FLAGS_HASH_ALL_SLAVES mlx5_ib_uapi_uar_alloc_type MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC mlx5_ib_uapi_reg mlx5_lib_caps MLX5_LIB_CAP_4K_UAR MLX5_LIB_CAP_DYN_UAR mlx5_ib_alloc_uctx_v2_flags MLX5_IB_ALLOC_UCTX_DEVX mlx5_ib_alloc_ucontext_req_v2 max_cqe_version mlx5_ib_alloc_ucontext_resp_mask MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG mlx5_user_cmds_supp_uhw MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE MLX5_USER_CMDS_SUPP_UHW_CREATE_AH mlx5_ib_alloc_ucontext_resp qp_tab_size bf_reg_size tot_bfregs max_sq_desc_sz max_rq_desc_sz max_send_wqebb max_srq_recv_wr flow_action_flags cmds_supp_uhw eth_min_inline clock_info_versions hca_core_clock_offset log_uar_size num_uars_per_page mlx5_ib_alloc_pd_resp mlx5_ib_tso_caps max_tso mlx5_ib_rss_caps mlx5_ib_cqe_comp_caps max_num supported_format mlx5_ib_packet_pacing_cap_flags MLX5_IB_PP_SUPPORT_BURST mlx5_packet_pacing_caps qp_rate_limit_min qp_rate_limit_max cap_flags mlx5_ib_mpw_caps MPW_RESERVED MLX5_IB_ALLOW_MPW MLX5_IB_SUPPORT_EMPW mlx5_ib_sw_parsing_offloads MLX5_IB_SW_PARSING MLX5_IB_SW_PARSING_CSUM MLX5_IB_SW_PARSING_LSO mlx5_ib_sw_parsing_caps sw_parsing_offloads mlx5_ib_striding_rq_caps min_single_stride_log_num_of_bytes max_single_stride_log_num_of_bytes min_single_wqe_log_num_of_strides max_single_wqe_log_num_of_strides mlx5_ib_dci_streams_caps max_log_num_concurent max_log_num_errored mlx5_ib_query_dev_resp_flags MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP mlx5_ib_tunnel_offloads MLX5_IB_TUNNELED_OFFLOADS_VXLAN MLX5_IB_TUNNELED_OFFLOADS_GRE MLX5_IB_TUNNELED_OFFLOADS_GENEVE MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP mlx5_ib_query_device_resp tso_caps cqe_comp_caps packet_pacing_caps mlx5_ib_support_multi_pkt_send_wqes sw_parsing_caps striding_rq_caps tunnel_offloads_caps dci_streams_caps reg_c0 MLX5_IB_CLOCK_INFO_V1 uverbs_methods_device UVERBS_METHOD_INVOKE_WRITE UVERBS_METHOD_INFO_HANDLES UVERBS_METHOD_QUERY_PORT UVERBS_METHOD_GET_CONTEXT UVERBS_METHOD_QUERY_CONTEXT UVERBS_METHOD_QUERY_GID_TABLE UVERBS_METHOD_QUERY_GID_ENTRY uverbs_methods_mr UVERBS_METHOD_DM_MR_REG UVERBS_METHOD_MR_DESTROY UVERBS_METHOD_ADVISE_MR UVERBS_METHOD_QUERY_MR UVERBS_METHOD_REG_DMABUF_MR mlx5_ib_var_alloc_attrs MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID mlx5_ib_var_obj_destroy_attrs MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE mlx5_ib_var_obj_methods MLX5_IB_METHOD_VAR_OBJ_ALLOC MLX5_IB_METHOD_VAR_OBJ_DESTROY mlx5_ib_uar_alloc_attrs MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID mlx5_ib_uar_obj_destroy_attrs MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE mlx5_ib_uar_obj_methods MLX5_IB_METHOD_UAR_OBJ_ALLOC MLX5_IB_METHOD_UAR_OBJ_DESTROY mlx5_ib_device_query_context_attrs MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX mlx5_ib_reg_dmabuf_mr_attrs MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS MLX5_IB_MMAP_OFFSET_START MLX5_IB_MMAP_OFFSET_END MLX5_IB_MMAP_CMD_SHIFT MLX5_IB_MMAP_CMD_MASK MLX5_TM_MAX_RNDV_MSG_SIZE MLX5_TM_MAX_SGE mlx5_ib_mw ibmw MLX5_MAX_DELAY_DROP_TIMEOUT_MS mlx5_ib_event_work MLX5_ATOMIC_SIZE_QP_8BYTES MLX5_VPORT_ACCESS_METHOD_MAD MLX5_VPORT_ACCESS_METHOD_HCA MLX5_VPORT_ACCESS_METHOD_NIC mlx5_reg_node_desc ib_max_vl_num __IB_MAX_VL_0 __IB_MAX_VL_0_1 __IB_MAX_VL_0_3 __IB_MAX_VL_0_7 __IB_MAX_VL_0_14 mlx5_vl_hw_cap MLX5_VL_HW_0 MLX5_VL_HW_0_1 MLX5_VL_HW_0_2 MLX5_VL_HW_0_3 MLX5_VL_HW_0_4 MLX5_VL_HW_0_5 MLX5_VL_HW_0_6 MLX5_VL_HW_0_7 MLX5_VL_HW_0_14 ib_mr_status_check IB_MR_CHECK_SIG_STATUS ib_mr_rereg_flags IB_MR_REREG_TRANS IB_MR_REREG_PD IB_MR_REREG_ACCESS IB_MR_REREG_SUPPORTED ib_umem_dmabuf first_sg first_sg_offset last_sg_trim mlx5_ifc_create_mkey_out_bits mkey_index MLX5_EN_RD MLX5_EN_WR MLX5_PROF_MASK_QP_SIZE MLX5_PROF_MASK_MR_CACHE mlx5_async_cbk_t mlx5_async_work mlx5_ib_uapi_reg_dmabuf_flags MLX5_IB_UAPI_REG_DMABUF_ACCESS_DATA_DIRECT mlx5_ib_alloc_mw num_klms mlx5_mkeys_page mlx5r_async_create_mkey MAX_PENDING_REG_MR mlx5_wqe_srq_next_seg next_wqe_index MLX5_SRQ_FLAG_SIGNATURE mlx5_ib_create_srq mlx5_ib_create_srq_resp mlx5_switchdev_event MLX5_SWITCHDEV_EVENT_PAIR MLX5_SWITCHDEV_EVENT_UNPAIR mlx5_eswitch_rep_ops get_proto_dev mlx5_ib_query_pd_attrs MLX5_IB_ATTR_QUERY_PD_HANDLE MLX5_IB_ATTR_QUERY_PD_RESP_PDN mlx5_ib_pd_methods MLX5_IB_METHOD_PD_QUERY mlx5_ib_device_methods MLX5_IB_METHOD_QUERY_PORT MLX5_IB_METHOD_GET_DATA_DIRECT_SYSFS_PATH mlx5_ib_query_port_attrs MLX5_IB_ATTR_QUERY_PORT_PORT_NUM MLX5_IB_ATTR_QUERY_PORT mlx5_ib_get_data_direct_sysfs_path_attrs MLX5_IB_ATTR_GET_DATA_DIRECT_SYSFS_PATH mlx5_ib_uapi_query_port_flags MLX5_IB_UAPI_QUERY_PORT_VPORT MLX5_IB_UAPI_QUERY_PORT_VPORT_VHCA_ID MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_RX MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_TX MLX5_IB_UAPI_QUERY_PORT_VPORT_REG_C0 MLX5_IB_UAPI_QUERY_PORT_ESW_OWNER_VHCA_ID mlx5_ib_uapi_query_port vport_vhca_id esw_owner_vhca_id vport_steering_icm_rx vport_steering_icm_tx mlx5_ifc_fpga_shell_caps_bits max_num_qps total_rcv_credits dc log_ddr_size max_fpga_qp_msg_size mlx5_ifc_fpga_cap_bits fpga_id fpga_device register_file_ver fpga_ctrl_modify access_reg_query_mode access_reg_modify_mode image_version image_date image_time shell_version shell_caps ieee_vendor_id sandbox_product_version sandbox_product_id sandbox_basic_caps sandbox_extended_caps_len sandbox_extended_caps_addr fpga_ddr_start_addr fpga_cr_space_start_addr fpga_ddr_size fpga_cr_space_size MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS MLX5_SET_HCA_CAP_OP_MOD_ODP MLX5_SET_HCA_CAP_OP_MOD_ATOMIC MLX5_SET_HCA_CAP_OP_MOD_ROCE MLX5_SET_HCA_CAP_OP_MOD_IPSEC MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION mlx5_ifc_odp_per_transport_service_cap_bits receive srq_receive mlx5_ifc_wqe_based_flow_table_cap_bits log_max_num_ste log_max_num_stc log_max_num_rtc log_max_num_header_modify_pattern rtc_hash_split_table rtc_linear_lookup_table stc_alloc_log_granularity stc_alloc_log_max ste_alloc_log_granularity ste_alloc_log_max rtc_reparse_mode rtc_index_mode rtc_log_depth_max ste_format stc_action_type header_insert_type header_remove_type trivial_match_definer rtc_max_num_hash_definer_gen_wqe access_index_mode ste_format_gen_wqe linear_match_definer_reg_c3 fdb_jump_to_tir_stc reserved_at_1c1 mlx5_ifc_esw_cap_bits merged_eswitch esw_manager_vport_number_valid reserved_at_61 esw_manager_vport_number mlx5_ifc_e_switch_cap_bits vport_svlan_strip vport_cvlan_strip vport_svlan_insert vport_cvlan_insert_if_not_exist vport_cvlan_insert_overwrite vport_cvlan_insert_always esw_shared_ingress_acl esw_uplink_ingress_acl root_ft_on_other_esw reserved_at_a esw_functions_changed ecpf_vport_exists counter_eswitch_affinity nic_vport_node_guid_modify nic_vport_port_guid_modify vxlan_encap_decap nvgre_encap_decap log_max_fdb_encap_uplink reserved_2b log_max_esw_sf esw_sf_base_id mlx5_ifc_debug_cap_bits core_dump_general core_dump_qp resource_dump stall_detect reserved_at_23 mlx5_ifc_odp_scheme_cap_bits page_prefetch dc_odp_caps mlx5_ifc_odp_cap_bits transport_page_fault_scheme_cap memory_page_fault_scheme_cap mem_page_fault reserved_at_601 mlx5_ifc_tls_cap_bits tls_1_2_aes_gcm_128 tls_1_3_aes_gcm_128 tls_1_2_aes_gcm_256 tls_1_3_aes_gcm_256 mlx5_ifc_ipsec_cap_bits ipsec_full_offload ipsec_crypto_offload ipsec_esn ipsec_crypto_esp_aes_gcm_256_encrypt ipsec_crypto_esp_aes_gcm_128_encrypt ipsec_crypto_esp_aes_gcm_256_decrypt ipsec_crypto_esp_aes_gcm_128_decrypt log_max_ipsec_offload min_log_ipsec_full_replay_window max_log_ipsec_full_replay_window mlx5_ifc_crypto_cap_bits synchronize_dek int_kek_manual int_kek_auto log_dek_max_alloc log_max_num_deks log_dek_granularity log_max_num_int_kek sw_wrapped_dek mlx5_ifc_hca_cap_union_bits cmd_hca_cap cmd_hca_cap_2 odp_cap atomic_caps roce_cap per_protocol_networking_offload_caps flow_table_nic_cap flow_table_eswitch_cap wqe_based_flow_table_cap esw_cap e_switch_cap qos_cap debug_cap fpga_cap tls_cap device_mem_cap virtio_emulation_cap macsec_cap crypto_cap ipsec_cap mlx5_ifc_query_hca_cap_out_bits mlx5_ifc_query_hca_cap_in_bits other_function ec_vf_function mlx5_ifc_query_esw_vport_context_in_bits mlx5_cap_mode HCA_CAP_OPMOD_GET_MAX HCA_CAP_OPMOD_GET_CUR __cache_work_func __mlx5_ib_add max_num_sg max_num_meta_sg __mlx5_ib_alloc_mr __mlx5_ib_cq_clean __mlx5_ib_dereg_mr __mlx5_ib_remove _mlx5_alloc_mkey_descs _mlx5_mr_cache_alloc add_keys alloc_cacheable_mr alloc_var_entry board_id_show current_access_flags target_access_flags can_use_umr_rereg_access clean_keys copy_resize_cqes cqb create_cq_user create_flow_rule_vport_sq create_gsi_ud_qp create_mkey_callback create_real_mr create_srq_kernel create_srq_user deallocate_uars delay_drop_handler delay_drop_timeout_read delay_drop_timeout_write delay_time_func delayed_cache_work_func fill_vport_icm_addr fw_pages_show generate_completions get_octo_len get_param get_port_state get_sw_cqe get_unchangeable_access_flags handle_alloc_dm_memic handle_alloc_dm_sw_icm handle_responder handle_single_completion hca_type_show hw_rev_show lag_event limit_read limit_write mkey_cache_ent_from_rb_key mlx5_alloc_integrity_descs mlx5_alloc_priv_descs mlx5_cmd_alloc_memic mlx5_cmd_dealloc_memic mlx5_cmd_dealloc_memic_op mlx5_free_priv_descs mlx5_get_cc_param_val mlx5_get_roce_udp_sport_min mlx5_get_vport_access_method mlx5_ib_add_gid mlx5_ib_add_outstanding_wr mlx5_ib_add_sub_dev mlx5_ib_advise_mr mlx5_ib_alloc_dm mlx5_ib_alloc_mr mlx5_ib_alloc_mr_integrity mlx5_ib_alloc_pd mlx5_ib_alloc_pi_mr mlx5_ib_alloc_ucontext mlx5_ib_arm_cq mlx5_ib_bind_slave_port mr_status mlx5_ib_check_mr_status mlx5_ib_cleanup mlx5_ib_cleanup_cong_debugfs mlx5_ib_cleanup_multiport_master mlx5_ib_cq_clean eqe mlx5_ib_cq_comp mlx5_ib_cq_event mlx5_ib_create_gsi mlx5_ib_create_mkey mlx5_ib_data_direct_bind mlx5_ib_data_direct_init mlx5_ib_data_direct_unbind mlx5_ib_dealloc_dm mw mlx5_ib_dealloc_mw mlx5_ib_dealloc_pd mlx5_ib_dealloc_transport_domain ibcontext mlx5_ib_dealloc_ucontext mlx5_ib_del_gid sub_dev mlx5_ib_del_sub_dev mlx5_ib_dereg_mr mlx5_ib_destroy_ah mlx5_ib_destroy_cq mlx5_ib_destroy_gsi mlx5_ib_destroy_srq mlx5_ib_dev_res_cleanup mlx5_ib_dev_res_cq_init mlx5_ib_dev_res_init mlx5_ib_dev_res_srq_init mlx5_ib_disable_lb mlx5_ib_disassociate_ucontext mlx5_ib_dm_mmap_free mlx5_ib_dmabuf_invalidate_cb mlx5_ib_enable_lb mlx5_ib_event mlx5_ib_event_slave_port mlx5_ib_free_srq_wqe mlx5_ib_fs_cleanup mlx5_ib_generate_wc mlx5_ib_get_cqe_size mlx5_ib_get_dma_mr mlx5_ib_get_ibdev_from_mpi ib_port_num mlx5_ib_get_native_port_mdev mlx5_ib_get_rep_netdev mlx5_ib_get_vf_config mlx5_ib_get_vf_guid mlx5_ib_get_vf_stats attr_mask mlx5_ib_gsi_modify_qp mlx5_ib_gsi_pkey_change mlx5_ib_gsi_post_recv mlx5_ib_gsi_post_send qp_attr qp_attr_mask qp_init_attr mlx5_ib_gsi_query_qp mlx5_ib_gsi_silent_drop mlx5_ib_handle_event mlx5_ib_handle_internal_error mlx5_ib_handler_MLX5_IB_METHOD_DM_MAP_OP_ADDR mlx5_ib_handler_MLX5_IB_METHOD_DM_QUERY mlx5_ib_handler_MLX5_IB_METHOD_GET_DATA_DIRECT_SYSFS_PATH mlx5_ib_handler_MLX5_IB_METHOD_PD_QUERY mlx5_ib_handler_MLX5_IB_METHOD_QUERY_PORT mlx5_ib_handler_MLX5_IB_METHOD_UAR_OBJ_ALLOC mlx5_ib_handler_MLX5_IB_METHOD_VAR_OBJ_ALLOC mlx5_ib_init mlx5_ib_init_cong_debugfs mlx5_ib_init_multiport_master sg_offset mlx5_ib_map_mr_sg data_sg_nents data_sg_offset meta_sg meta_sg_nents meta_sg_offset mlx5_ib_map_mr_sg_pi mlx5_ib_map_mtt_mr_sg_pi mlx5_ib_mcg_attach mlx5_ib_mcg_detach mlx5_ib_mmap mlx5_ib_mmap_free cq_count mlx5_ib_modify_cq mlx5_ib_modify_device mlx5_ib_modify_port mlx5_ib_modify_srq mlx5_ib_poll_cq mlx5_ib_port_link_layer mlx5_ib_post_recv_nodrain mlx5_ib_post_send_nodrain mlx5_ib_post_srq_recv mlx5_ib_put_native_port_mdev uhw mlx5_ib_query_device mlx5_ib_query_gid mlx5_ib_query_pkey mlx5_ib_query_port srq_attr mlx5_ib_query_srq mlx5_ib_query_ucontext mlx5_ib_reg_dm_mr mlx5_ib_reg_user_mr mlx5_ib_reg_user_mr_dmabuf mlx5_ib_rep_query_pkey mlx5_ib_rep_query_port mlx5_ib_rep_to_dev new_access_flags new_pd mlx5_ib_rereg_user_mr mlx5_ib_revoke_data_direct_mrs mlx5_ib_rn_get_params mlx5_ib_roce_cleanup mlx5_ib_roce_init mlx5_ib_set_cc_param_mask_val mlx5_ib_set_vf_guid mlx5_ib_set_vf_link_state sg_offset_p meta_sgl meta_sg_offset_p mlx5_ib_sg_to_klms mlx5_ib_srq_event mlx5_ib_stage_bfrag_cleanup mlx5_ib_stage_bfrag_init mlx5_ib_stage_caps_cleanup mlx5_ib_stage_caps_init mlx5_ib_stage_cong_debugfs_cleanup mlx5_ib_stage_cong_debugfs_init mlx5_ib_stage_delay_drop_cleanup mlx5_ib_stage_delay_drop_init mlx5_ib_stage_dev_notifier_cleanup mlx5_ib_stage_dev_notifier_init mlx5_ib_stage_ib_reg_cleanup mlx5_ib_stage_ib_reg_init mlx5_ib_stage_init_cleanup mlx5_ib_stage_init_init mlx5_ib_stage_non_default_cb mlx5_ib_stage_post_ib_reg_umr_init mlx5_ib_stage_pre_ib_reg_umr_cleanup mlx5_ib_stage_raw_eth_non_default_cb mlx5_ib_stage_uar_cleanup mlx5_ib_stage_uar_init mlx5_ib_unbind_slave_port mlx5_ib_vport_rep_load mlx5_ib_vport_rep_unload mlx5_mkey_cache_cleanup mlx5_mkey_cache_init mlx5_mr_cache_alloc mlx5_netdev_event cur_qp mlx5_poll_one mlx5_port_immutable mlx5_port_rep_immutable mlx5_query_hca_port mlx5_query_port_roce mlx5_set_page mlx5_set_page_pi mlx5e_mdev_notifier_event persistent_entry mlx5r_cache_create_ent_locked mlx5r_deref_odp_mkey mlx5r_destroy_cache_entries mlx5r_handle_mkey_cleanup mlx5r_mkeys_uninit mlx5r_mp_probe mlx5r_mp_remove mlx5r_probe mlx5r_remove mlx5r_rep_cleanup mlx5r_rep_init mlx5r_rep_probe mlx5r_rep_remove mmap_obj_cleanup notify_soft_wc_handler pkey_change_handler is_fatal_err poll_soft_wc pop_mkey_locked push_mkey_locked queue_adjust_cache_locked reg_create crossed_lkey reg_create_crossing_vhca_mr reg_pages_show limit_fill resize_available_mrs mkc set_cache_mkc set_mkc_access_pd_addr_fields set_param set_port_caps_atomic set_roce_addr set_ucontext_resp qp_index setup_qp size_read size_write npolled is_send sw_comp uar_mmap new_umem umr_rereg_pas var_is_supported ib_stat_flag IB_STAT_FLAG_OPTIONAL ib_counters_description IB_COUNTER_PACKETS IB_COUNTER_BYTES mlx5_ifc_query_q_counter_in_bits mlx5_ifc_dealloc_q_counter_in_bits mlx5_ifc_alloc_q_counter_out_bits mlx5_ifc_alloc_q_counter_in_bits mlx5_ifc_pcam_enhanced_features_bits fec_200G_per_lane_in_pplm fec_100G_per_lane_in_pplm reserved_at_49 fec_50G_per_lane_in_pplm rx_icrc_encapsulated_counter reserved_at_6e ptys_extended_ethernet pfcc_mask reserved_at_77 per_lane_error_counters rx_buffer_fullness_counters ptys_connector_type reserved_at_7d ppcnt_discard_group ppcnt_statistical_group mlx5_ifc_pcam_regs_5000_to_507f_bits port_access_reg_cap_mask_127_to_96 port_access_reg_cap_mask_95_to_64 port_access_reg_cap_mask_63_to_36 pplm port_access_reg_cap_mask_34_to_32 port_access_reg_cap_mask_31_to_13 pbmc pptb port_access_reg_cap_mask_10_to_09 ppcnt port_access_reg_cap_mask_07_to_00 regs_5000_to_507f enhanced_features mlx5_ifc_pcam_reg_bits feature_group access_reg_group port_access_reg_cap_mask feature_cap_mask mlx5_ib_counter user_virt rdma_nldev_attr RDMA_NLDEV_ATTR_UNSPEC RDMA_NLDEV_ATTR_PAD RDMA_NLDEV_ATTR_DEV_INDEX RDMA_NLDEV_ATTR_DEV_NAME RDMA_NLDEV_ATTR_PORT_INDEX RDMA_NLDEV_ATTR_CAP_FLAGS RDMA_NLDEV_ATTR_FW_VERSION RDMA_NLDEV_ATTR_NODE_GUID RDMA_NLDEV_ATTR_SYS_IMAGE_GUID RDMA_NLDEV_ATTR_SUBNET_PREFIX RDMA_NLDEV_ATTR_LID RDMA_NLDEV_ATTR_SM_LID RDMA_NLDEV_ATTR_LMC RDMA_NLDEV_ATTR_PORT_STATE RDMA_NLDEV_ATTR_PORT_PHYS_STATE RDMA_NLDEV_ATTR_DEV_NODE_TYPE RDMA_NLDEV_ATTR_RES_SUMMARY RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_NAME RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_CURR RDMA_NLDEV_ATTR_RES_QP RDMA_NLDEV_ATTR_RES_QP_ENTRY RDMA_NLDEV_ATTR_RES_LQPN RDMA_NLDEV_ATTR_RES_RQPN RDMA_NLDEV_ATTR_RES_RQ_PSN RDMA_NLDEV_ATTR_RES_SQ_PSN RDMA_NLDEV_ATTR_RES_PATH_MIG_STATE RDMA_NLDEV_ATTR_RES_TYPE RDMA_NLDEV_ATTR_RES_STATE RDMA_NLDEV_ATTR_RES_PID RDMA_NLDEV_ATTR_RES_KERN_NAME RDMA_NLDEV_ATTR_RES_CM_ID RDMA_NLDEV_ATTR_RES_CM_ID_ENTRY RDMA_NLDEV_ATTR_RES_PS RDMA_NLDEV_ATTR_RES_SRC_ADDR RDMA_NLDEV_ATTR_RES_DST_ADDR RDMA_NLDEV_ATTR_RES_CQ RDMA_NLDEV_ATTR_RES_CQ_ENTRY RDMA_NLDEV_ATTR_RES_CQE RDMA_NLDEV_ATTR_RES_USECNT RDMA_NLDEV_ATTR_RES_POLL_CTX RDMA_NLDEV_ATTR_RES_MR RDMA_NLDEV_ATTR_RES_MR_ENTRY RDMA_NLDEV_ATTR_RES_RKEY RDMA_NLDEV_ATTR_RES_LKEY RDMA_NLDEV_ATTR_RES_IOVA RDMA_NLDEV_ATTR_RES_MRLEN RDMA_NLDEV_ATTR_RES_PD RDMA_NLDEV_ATTR_RES_PD_ENTRY RDMA_NLDEV_ATTR_RES_LOCAL_DMA_LKEY RDMA_NLDEV_ATTR_RES_UNSAFE_GLOBAL_RKEY RDMA_NLDEV_ATTR_NDEV_INDEX RDMA_NLDEV_ATTR_NDEV_NAME RDMA_NLDEV_ATTR_DRIVER RDMA_NLDEV_ATTR_DRIVER_ENTRY RDMA_NLDEV_ATTR_DRIVER_STRING RDMA_NLDEV_ATTR_DRIVER_PRINT_TYPE RDMA_NLDEV_ATTR_DRIVER_S32 RDMA_NLDEV_ATTR_DRIVER_U32 RDMA_NLDEV_ATTR_DRIVER_S64 RDMA_NLDEV_ATTR_DRIVER_U64 RDMA_NLDEV_ATTR_RES_PDN RDMA_NLDEV_ATTR_RES_CQN RDMA_NLDEV_ATTR_RES_MRN RDMA_NLDEV_ATTR_RES_CM_IDN RDMA_NLDEV_ATTR_RES_CTXN RDMA_NLDEV_ATTR_LINK_TYPE RDMA_NLDEV_SYS_ATTR_NETNS_MODE RDMA_NLDEV_ATTR_DEV_PROTOCOL RDMA_NLDEV_NET_NS_FD RDMA_NLDEV_ATTR_CHARDEV_TYPE RDMA_NLDEV_ATTR_CHARDEV_NAME RDMA_NLDEV_ATTR_CHARDEV_ABI RDMA_NLDEV_ATTR_CHARDEV RDMA_NLDEV_ATTR_UVERBS_DRIVER_ID RDMA_NLDEV_ATTR_STAT_MODE RDMA_NLDEV_ATTR_STAT_RES RDMA_NLDEV_ATTR_STAT_AUTO_MODE_MASK RDMA_NLDEV_ATTR_STAT_COUNTER RDMA_NLDEV_ATTR_STAT_COUNTER_ENTRY RDMA_NLDEV_ATTR_STAT_COUNTER_ID RDMA_NLDEV_ATTR_STAT_HWCOUNTERS RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY_NAME RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY_VALUE RDMA_NLDEV_ATTR_DEV_DIM RDMA_NLDEV_ATTR_RES_RAW RDMA_NLDEV_ATTR_RES_CTX RDMA_NLDEV_ATTR_RES_CTX_ENTRY RDMA_NLDEV_ATTR_RES_SRQ RDMA_NLDEV_ATTR_RES_SRQ_ENTRY RDMA_NLDEV_ATTR_RES_SRQN RDMA_NLDEV_ATTR_MIN_RANGE RDMA_NLDEV_ATTR_MAX_RANGE RDMA_NLDEV_SYS_ATTR_COPY_ON_FORK RDMA_NLDEV_ATTR_STAT_HWCOUNTER_INDEX RDMA_NLDEV_ATTR_STAT_HWCOUNTER_DYNAMIC RDMA_NLDEV_SYS_ATTR_PRIVILEGED_QKEY_MODE RDMA_NLDEV_ATTR_DRIVER_DETAILS RDMA_NLDEV_ATTR_RES_SUBTYPE RDMA_NLDEV_ATTR_DEV_TYPE RDMA_NLDEV_ATTR_PARENT_NAME RDMA_NLDEV_ATTR_NAME_ASSIGN_TYPE RDMA_NLDEV_ATTR_EVENT_TYPE RDMA_NLDEV_SYS_ATTR_MONITOR_MODE RDMA_NLDEV_ATTR_MAX mlx5_sgmt_type MLX5_SGMT_TYPE_HW_CQPC MLX5_SGMT_TYPE_HW_SQPC MLX5_SGMT_TYPE_HW_RQPC MLX5_SGMT_TYPE_FULL_SRQC MLX5_SGMT_TYPE_FULL_CQC MLX5_SGMT_TYPE_FULL_EQC MLX5_SGMT_TYPE_FULL_QPC MLX5_SGMT_TYPE_SND_BUFF MLX5_SGMT_TYPE_RCV_BUFF MLX5_SGMT_TYPE_SRQ_BUFF MLX5_SGMT_TYPE_CQ_BUFF MLX5_SGMT_TYPE_EQ_BUFF MLX5_SGMT_TYPE_SX_SLICE MLX5_SGMT_TYPE_SX_SLICE_ALL MLX5_SGMT_TYPE_RDB MLX5_SGMT_TYPE_RX_SLICE_ALL MLX5_SGMT_TYPE_PRM_QUERY_QP MLX5_SGMT_TYPE_PRM_QUERY_CQ MLX5_SGMT_TYPE_PRM_QUERY_MKEY MLX5_SGMT_TYPE_MENU MLX5_SGMT_TYPE_TERMINATE MLX5_SGMT_TYPE_NUM mlx5_rsc_key index1 index2 num_of_obj1 num_of_obj2 mlx5_rsc_dump_cmd ib_uverbs_advise_mr_flag IB_UVERBS_ADVISE_MR_FLAG_FLUSH mlx5_ifc_trans_page_fault_info_bits page_fault_type wq_number fault_token mlx5_ifc_mem_page_fault_info_bits fault_token_47_32 fault_token_31_0 mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits trans_page_fault_info mem_page_fault_info mlx5_ifc_page_fault_resume_in_bits page_fault_info MLX5_PFAULT_SUBTYPE_WQE MLX5_PFAULT_SUBTYPE_RDMA MLX5_PFAULT_SUBTYPE_MEMORY wqe_page_fault_type MLX5_WQE_PF_TYPE_RMP MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE MLX5_WQE_PF_TYPE_RESP MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC mlx5_eq_param mlx5_irq mlx5_pagefault_type_flags MLX5_PFAULT_REQUESTOR MLX5_PFAULT_WRITE MLX5_PFAULT_RDMA mlx5_base_av fault_byte_count prefetch_before_byte_count prefetch_after_byte_count mlx5_pagefault event_subtype pf_frame io_virt bcnt MLX5_IB_NUM_PF_EQE MLX5_IB_NUM_PF_DRAIN prefetch_mr_work pf_flags uverbs_obj_fd_type mlx5_ib_devx_methods MLX5_IB_METHOD_DEVX_OTHER MLX5_IB_METHOD_DEVX_QUERY_UAR MLX5_IB_METHOD_DEVX_QUERY_EQN MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT mlx5_ib_devx_other_attrs MLX5_IB_ATTR_DEVX_OTHER_CMD_IN MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT mlx5_ib_devx_obj_create_attrs MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT mlx5_ib_devx_query_uar_attrs MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX mlx5_ib_devx_obj_destroy_attrs MLX5_IB_ATTR_DEVX_OBJ_DESTROY_HANDLE mlx5_ib_devx_obj_modify_attrs MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT mlx5_ib_devx_obj_query_attrs MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT mlx5_ib_devx_obj_query_async_attrs MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_HANDLE MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN mlx5_ib_devx_subscribe_event_attrs MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE mlx5_ib_devx_query_eqn_attrs MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN mlx5_ib_devx_obj_methods MLX5_IB_METHOD_DEVX_OBJ_CREATE MLX5_IB_METHOD_DEVX_OBJ_DESTROY MLX5_IB_METHOD_DEVX_OBJ_MODIFY MLX5_IB_METHOD_DEVX_OBJ_QUERY MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY mlx5_ib_devx_umem_reg_attrs MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR MLX5_IB_ATTR_DEVX_UMEM_REG_LEN MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP MLX5_IB_ATTR_DEVX_UMEM_REG_DMABUF_FD mlx5_ib_devx_umem_dereg_attrs MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE mlx5_ib_devx_umem_methods MLX5_IB_METHOD_DEVX_UMEM_REG MLX5_IB_METHOD_DEVX_UMEM_DEREG mlx5_ib_devx_async_cmd_fd_alloc_attrs MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE mlx5_ib_devx_async_event_fd_alloc_attrs MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS mlx5_ib_devx_async_cmd_fd_methods MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC mlx5_ib_devx_async_event_fd_methods MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC mlx5_ib_uapi_devx_async_cmd_hdr out_data mlx5_ib_uapi_devx_create_event_channel_flags MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA mlx5_ib_uapi_devx_async_event_hdr MLX5_OBJ_TYPE_SW_ICM MLX5_OBJ_TYPE_GENEVE_TLV_OPT MLX5_OBJ_TYPE_VIRTIO_NET_Q MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS MLX5_OBJ_TYPE_MATCH_DEFINER MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT MLX5_OBJ_TYPE_STC MLX5_OBJ_TYPE_RTC MLX5_OBJ_TYPE_STE MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN MLX5_OBJ_TYPE_PAGE_TRACK MLX5_OBJ_TYPE_MKEY MLX5_OBJ_TYPE_QP MLX5_OBJ_TYPE_PSV MLX5_OBJ_TYPE_RMP MLX5_OBJ_TYPE_XRC_SRQ MLX5_OBJ_TYPE_RQ MLX5_OBJ_TYPE_SQ MLX5_OBJ_TYPE_TIR MLX5_OBJ_TYPE_TIS MLX5_OBJ_TYPE_DCT MLX5_OBJ_TYPE_XRQ MLX5_OBJ_TYPE_RQT MLX5_OBJ_TYPE_FLOW_COUNTER MLX5_OBJ_TYPE_CQ MLX5_OBJ_TYPE_FT_ALIAS MLX5_CMD_OP_GENERAL_START MLX5_CMD_OP_GENERAL_END MLX5_UCTX_CAP_RAW_TX MLX5_UCTX_CAP_INTERNAL_DEV_RES mlx5_ifc_dest_format_struct_bits destination_eswitch_owner_vhca_id_valid packet_reformat destination_table_type destination_eswitch_owner_vhca_id mlx5_ifc_flow_counter_list_bits mlx5_ifc_extended_dest_format_bits destination_entry packet_reformat_id mlx5_ifc_dest_format_flow_counter_list_auto_bits extended_dest_format flow_counter_list mlx5_ifc_mac_address_layout_bits mac_addr_47_32 mac_addr_31_0 mlx5_ifc_vlan_bits cfi mlx5_ifc_exe_aso_ctrl_flow_meter_bits aso_type meter_id mlx5_ifc_exe_aso_ctrl exe_aso_ctrl_flow_meter mlx5_ifc_execute_aso_bits aso_object_id exe_aso_ctrl mlx5_ifc_flow_context_bits extended_destination uplink_hairpin_en encrypt_decrypt_type destination_list_size flow_counter_list_size modify_header_id encrypt_decrypt_obj_id reserved_at_1300 mlx5_ifc_tsar_element_bits tsar_type mlx5_ifc_vport_element_bits eswitch_owner_vhca_id_valid eswitch_owner_vhca_id mlx5_ifc_vport_tc_element_bits mlx5_ifc_element_attributes_bits tsar vport_tc mlx5_ifc_scheduling_context_bits element_type element_attributes parent_element_id bw_share max_average_bw max_bw_obj_id mlx5_ifc_set_l2_table_entry_in_bits silent_mode_valid reserved_at_f2 vlan_valid mlx5_ifc_set_fte_in_bits modify_enable_mask flow_index mlx5_ifc_query_tis_in_bits mlx5_ifc_query_tir_in_bits mlx5_ifc_query_sq_in_bits mlx5_ifc_query_scheduling_element_in_bits scheduling_hierarchy scheduling_element_id mlx5_ifc_query_rqt_in_bits mlx5_ifc_query_rq_in_bits mlx5_ifc_query_mkey_in_bits mlx5_ifc_query_l2_table_entry_in_bits mlx5_ifc_sw_owner_icm_root_params_bits sw_owner_icm_root_1 sw_owner_icm_root_0 mlx5_ifc_rtc_params_bits rtc_id_0 rtc_id_1 sws hws mlx5_ifc_flow_table_context_bits reformat_en decap_en table_miss_action rtc_valid table_miss_id lag_master_next_table_id mlx5_ifc_query_flow_table_in_bits mlx5_ifc_query_fte_in_bits mlx5_ifc_general_obj_out_cmd_hdr_bits mlx5_ifc_query_flow_group_in_bits mlx5_ifc_query_flow_counter_in_bits num_of_counters mlx5_ifc_query_packet_reformat_context_in_bits mlx5_ifc_alloc_packet_reformat_context_out_bits mlx5_ifc_dealloc_packet_reformat_context_in_bits reserved_20 reserved_60 mlx5_ifc_alloc_modify_header_context_out_bits mlx5_ifc_dealloc_modify_header_context_in_bits mlx5_ifc_query_modify_header_context_in_bits mlx5_ifc_query_cq_in_bits mlx5_ifc_modify_tir_bitmask_bits self_lb_en reserved_at_3c reserved_at_3e packet_merge mlx5_ifc_modify_tir_in_bits mlx5_ifc_modify_scheduling_element_in_bits scheduling_context mlx5_ifc_rqt_bitmask_bits rqn_list mlx5_ifc_modify_rqt_in_bits mlx5_ifc_destroy_scheduling_element_in_bits mlx5_ifc_destroy_psv_in_bits psvn mlx5_ifc_destroy_mkey_in_bits mlx5_ifc_destroy_flow_group_in_bits mlx5_ifc_destroy_cq_in_bits mlx5_ifc_delete_vxlan_udp_dport_in_bits vxlan_udp_port mlx5_ifc_delete_l2_table_entry_in_bits mlx5_ifc_delete_fte_in_bits mlx5_ifc_create_tis_out_bits mlx5_ifc_create_scheduling_element_out_bits mlx5_ifc_create_scheduling_element_in_bits mlx5_ifc_create_rqt_out_bits mlx5_ifc_create_rq_out_bits mlx5_ifc_create_psv_out_bits psv0_index psv1_index psv2_index psv3_index mlx5_ifc_create_psv_in_bits num_psv mlx5_ifc_create_flow_table_out_bits mlx5_ifc_create_flow_table_in_bits flow_table_context mlx5_ifc_create_flow_group_out_bits mlx5_ifc_create_cq_out_bits mlx5_ifc_arm_xrq_in_bits mlx5_ifc_alloc_flow_counter_out_bits mlx5_ifc_alloc_flow_counter_in_bits flow_counter_bulk_log_size flow_counter_bulk mlx5_ifc_add_vxlan_udp_dport_in_bits mlx5_ifc_mtt_bits ptag_63_32 ptag_31_8 wr_en rd_en mlx5_ifc_modify_flow_table_in_bits mlx5_ifc_umem_bits num_of_mtt mtt mlx5_ifc_uctx_bits mlx5_ifc_create_umem_in_bits mlx5_ifc_create_umem_out_bits umem_id mlx5_ifc_destroy_umem_in_bits mlx5_ifc_create_uctx_in_bits mlx5_ifc_create_uctx_out_bits mlx5_ifc_destroy_uctx_in_bits mlx5_ifc_affiliated_event_header_bits devx_obj_flags DEVX_OBJ_FLAGS_INDIRECT_MKEY DEVX_OBJ_FLAGS_DCT DEVX_OBJ_FLAGS_CQ DEVX_OBJ_FLAGS_HW_FREED mlx5_async_cmd devx_async_data ev_file cmd_out_len devx_async_cmd_event_file uobj ev_queue devx_async_event_data devx_event unaffiliated_list devx_obj_event obj_sub_list devx_event_subscription file_list xa_list is_cleaned xa_key_level1 xa_key_level2 devx_async_event_file subscribed_events_list omit_data is_overflow_err is_destroyed devx_umem devx_umem_reg_cmd devx_async_event_queue bytes_in_use __mlx5_ib_alloc_counters pgsz_bitmap page_offset_bits pgoff_bitmask page_offset_quantized __mlx5_umem_find_best_quantized_pgoff alloc_implicit_mr_null_mkey deliver_event devx_async_cmd_event_destroy_uobj devx_async_cmd_event_poll devx_async_cmd_event_read devx_async_destroy_cb devx_async_event_destroy_uobj devx_async_event_poll devx_async_event_read devx_cleanup_subscription devx_cq_comp devx_event_notifier devx_free_subscription devx_get_created_obj_id devx_get_obj_id devx_get_uid devx_is_obj_query_cmd devx_is_supported devx_is_valid_obj_id din devx_obj_build_destroy_cmd devx_obj_cleanup devx_query_callback devx_set_umem_valid devx_umem_cleanup devx_umem_get devx_umem_reg_cmd_alloc do_alloc_stats do_get_hw_stats do_get_op_stat dump_rsc fill_res_raw find_odp_mkey free_implicit_child_mr_work get_counters get_prefetchable_mr implicit_get_child_mr internal_fill_odp_caps mlx5_ib_advise_mr_prefetch mlx5_ib_alloc_hw_device_stats mlx5_ib_alloc_hw_port_stats mlx5_ib_alloc_implicit_mr mlx5_ib_counter_alloc_stats mlx5_ib_counter_bind_qp mlx5_ib_counter_dealloc mlx5_ib_counter_unbind_qp mlx5_ib_counter_update_stats mlx5_ib_counters_cleanup mlx5_ib_counters_clear_description mlx5_ib_counters_init mlx5_ib_create_counters mlx5_ib_db_map_user mlx5_ib_db_unmap_user mlx5_ib_dealloc_counters mlx5_ib_destroy_counters mlx5_ib_devx_cleanup is_user mlx5_ib_devx_create mlx5_ib_devx_destroy mlx5_ib_devx_init mlx5_ib_eq_pf_action mlx5_ib_eq_pf_int mlx5_ib_eq_pf_process mlx5_ib_eqe_pf_action mlx5_ib_fill_counters mlx5_ib_flow_counters_set_data mlx5_ib_free_odp_mr mlx5_ib_get_counters_id mlx5_ib_get_hw_stats mlx5_ib_handler_MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC mlx5_ib_handler_MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OBJ_CREATE mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OBJ_MODIFY mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OBJ_QUERY mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OTHER mlx5_ib_handler_MLX5_IB_METHOD_DEVX_QUERY_EQN mlx5_ib_handler_MLX5_IB_METHOD_DEVX_QUERY_UAR mlx5_ib_handler_MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT mlx5_ib_handler_MLX5_IB_METHOD_DEVX_UMEM_REG mlx5_ib_init_dmabuf_mr mlx5_ib_init_odp_mr mni mlx5_ib_invalidate_range mlx5_ib_modify_stat pfault mlx5_ib_mr_memory_pfault_handler mlx5_ib_mr_rdma_pfault_handler mlx5_ib_mr_wqe_pfault_handler mlx5_ib_odp_cleanup_one mlx5_ib_odp_init mlx5_ib_odp_init_one mlx5_ib_page_fault_resume mlx5_ib_populate_pas mlx5_ib_prefetch_mr_work mlx5_ib_query_ext_ppcnt_counters mlx5_ib_query_q_counters mlx5_ib_query_q_counters_vport read_attr mlx5_ib_read_counters mlx5_ib_restrack_init mlx5_ib_ufile_hw_cleanup mlx5_odp_init_mkey_cache xlt mlx5_odp_populate_xlt mlx5r_odp_create_eq bytes_mapped pagefault_dmabuf_mr odp_imr user_va pagefault_implicit_mr permissive_fault pagefault_mr odp pagefault_real_mr pagefault_single_data_segment read_flow_counters __mlx5_ib_modify_qp __mlx5_ib_qp_set_counter __mlx5_ib_qp_set_raw_qp_counter __set_srq_page_size _create_kernel_qp _create_user_qp _mlx5r_umr_update_mr_pas dyn_bfreg bfregn_to_uar_index calc_sq_size create_dci create_dct create_kernel_qp create_raw_packet_qp qpin create_raw_packet_qp_rq create_raw_packet_qp_sq qp_flags_en create_raw_packet_qp_tir create_raw_packet_qp_tis create_rmp_cmd rwq create_rq create_rss_raw_qp_tir create_srq_cmd create_user_qp create_user_rq create_xrc_srq_cmd create_xrc_tgt_qp create_xrq_cmd destroy_qp_common get_macsec_device get_pas_size get_qp_ts_format srqc get_srqc get_tx_affinity get_tx_affinity_rr get_wq sdrain handle_drain_completion macsec_event mlx5_cleanup_srq_table mlx5_cmd_alloc_transport_domain is_srq mlx5_cmd_arm_srq mlx5_cmd_attach_mcg mlx5_cmd_create_srq mlx5_cmd_dealloc_pd mlx5_cmd_dealloc_transport_domain mlx5_cmd_destroy_rqt mlx5_cmd_destroy_srq mlx5_cmd_destroy_tir mlx5_cmd_destroy_tis mlx5_cmd_detach_mcg mlx5_cmd_get_srq __inb __outb opmod mlx5_cmd_mad_ifc cong_point mlx5_cmd_query_cong_params mlx5_cmd_query_srq out_vuid mlx5_cmd_query_vuid uarn mlx5_cmd_uar_alloc mlx5_cmd_uar_dealloc mlx5_cmd_xrcd_alloc mlx5_cmd_xrcd_dealloc mlx5_ib_alloc_xrcd mlx5_ib_create_rwq_ind_table mlx5_ib_dealloc_xrcd mlx5_ib_destroy_dct mlx5_ib_destroy_qp mlx5_ib_destroy_rwq_ind_table mlx5_ib_destroy_wq mlx5_ib_drain_qp_done mlx5_ib_drain_rq mlx5_ib_drain_sq mlx5_ib_free_bfreg mlx5_ib_handle_qp_event mlx5_ib_handler_MLX5_IB_METHOD_PP_OBJ_ALLOC mlx5_ib_lock_cqs mlx5_ib_modify_dct wq_attr wq_attr_mask mlx5_ib_qp_event mlx5_ib_qp_event_cleanup mlx5_ib_qp_event_init mlx5_ib_qp_set_counter mlx5_ib_query_qp mlx5_ib_read_kernel_wqe_sq wq_offset wq_wqe_cnt wq_wqe_shift bytes_copied mlx5_ib_read_user_wqe_common mlx5_ib_read_wqe_rq mlx5_ib_read_wqe_sq mlx5_ib_read_wqe_srq mlx5_ib_unlock_cqs mlx5_ib_wq_event mlx5_init_srq_table macsec_device mlx5_macsec_save_roce_gid mlx5_set_path mlx5r_add_gid_macsec_operations mlx5r_cmd_query_special_mkeys mlx5r_del_gid_macsec_operations mlx5r_ib_rate mlx5r_macsec_dealloc_gids mlx5r_macsec_event_register mlx5r_macsec_event_unregister mlx5r_macsec_init_gids_and_devlist mlx5r_umr_alloc_xlt mlx5r_umr_cleanup mlx5r_umr_create_xlt mlx5r_umr_done mlx5r_umr_final_update_xlt mlx5r_umr_free_xlt mlx5r_umr_init with_data mlx5r_umr_post_send mlx5r_umr_post_send_wait mlx5r_umr_qp_rst2rts umr_context mlx5r_umr_recover mlx5r_umr_rereg_pd_access mlx5r_umr_resource_cleanup mlx5r_umr_resource_init mlx5r_umr_revoke_mr mlx5r_umr_set_access_flags mlx5r_umr_set_update_xlt_mkey_seg mlx5r_umr_update_data_direct_ksm_pas mlx5r_umr_update_mr_pas mlx5r_umr_update_xlt raw_qp_param tx_affinity modify_raw_packet_qp modify_raw_packet_qp_sq pp_is_supported pp_obj_cleanup process_create_flag process_create_flags process_vendor_flag process_vendor_flags query_qp_attr rdma_gid2ip set_rq_size set_srqc set_user_buf_size set_wq sq_overhead srq_event_notifier to_mlx5_st to_rdma_ah_attr validate_rd_atomic